PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 232

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
TABLE 17-4:
17.2.9
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than three
seconds per month.
To perform this calibration, find the number of error
clock pulses and store the value into the lower half of
the RTCCAL register. The 8-bit, signed value, loaded
into RTCCAL, is multiplied by four and will be either
added or subtracted from the RTCC timer, once every
minute.
To calibrate the RTCC module:
1.
2.
EQUATION 17-1:
3.
DS39957D-page 232
ALRMPTR<1:0>
(Ideal Frequency (32,758) – Measured Frequency) * 60 =
Error Clocks per Minute
Use another timer resource on the device to find
the error of the 32.768 kHz crystal.
Convert the number of error clock pulses per
minute (see
• If the oscillator is faster than ideal (negative
• If the oscillator is slower than ideal (positive
Load the RTCCAL register with the correct
value.
result from Step 2), the RCFGCALL register
value needs to be negative. This causes the
specified number of clock pulses to be
subtracted from the timer counter, once every
minute.
result from Step 2), the RCFGCALL register
value needs to be positive. This causes the
specified number of clock pulses to be added to
the timer counter, once every minute.
00
01
10
11
CALIBRATION
Equation
ALRMVAL REGISTER
MAPPING
Alarm Value Register Window
ALRMMNTH
ALRMVALH
ALRMMIN
ALRMWD
CONVERTING ERROR
CLOCK PULSES
—
17-1).
ALRMVALL
ALRMSEC
ALRMDAY
ALRMHR
—
Writes to the RTCCAL register should occur only when
the timer is turned off or immediately after the rising
edge of the seconds pulse.
17.3
The Alarm features and characteristics are:
• Configurable from half a second to one year
• Enabled using the ALRMEN bit (ALRMCFG<7>,
• Offers one-time and repeat alarm options
17.3.1
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. The bit will
not be cleared if the CHIME bit = 1 or if ALRMRPT  0.
The interval selection of the alarm is configured
through the ALRMCFG bits (AMASK<3:0>) (see
Figure
many, digits of the alarm must match the clock value for
the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The number of times this
occurs, after the alarm is enabled, is stored in the
ALRMRPT register.
Note:
Register
Note:
17-5). These bits determine which, and how
Alarm
17-4)
In determining the crystal’s error value, it
is the user’s responsibility to include the
crystal’s initial error from drift due to
temperature or crystal aging.
CONFIGURING THE ALARM
While the alarm is enabled (ALRMEN = 1),
changing any of the registers, other than
the RTCCAL, ALRMCFG and ALRMRPT
registers and the CHIME bit, can result in a
false alarm event leading to a false alarm
interrupt. To avoid this, only change the
timer and alarm values while the alarm is
disabled (ALRMEN = 0). It is recommended
that the ALRMCFG and ALRMRPT regis-
ters and CHIME bit be changed when
RTCSYNC = 0.
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