PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 271

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

19.4.8
In Sleep mode, all clock sources are disabled.
Timer2/4/6/8 will not increment and the state of the
module will not change. If the ECCPx pin is driving a
value, it will continue to drive that value. When the
device wakes up, it will continue from this state. If
Two-Speed Start-ups are enabled, the initial start-up
frequency from HF-INTOSC and the postscaler may
not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
 2009-2011 Microchip Technology Inc.
OPERATION IN POWER-MANAGED
MODES
PIC18F87K90 FAMILY
19.4.8.1
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2/4/6/8
register will be set. The ECCPx will then be clocked from
the internal oscillator clock source, which may have a
different clock frequency than the primary clock.
19.4.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states. This forces the ECCP module to reset to
a state compatible with previous, non-Enhanced CCP
modules used on other PIC18 and PIC16 devices.
EFFECTS OF A RESET
Operation with Fail-Safe
Clock Monitor (FSCM)
DS39957D-page 271