PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 372

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
22.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS39957D-page 372
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTA1
RCREG1
TXSTA1
BAUDCON1
SPBRGH1
SPBRG1
RCSTA2
RCREG2
TXSTA2
BAUDCON2
SPBRGH2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Name
EUSART SYNCHRONOUS SLAVE
RECEPTION
EUSART1 Receive Register
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
EUSART2 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
TMR5GIF
TMR5GIE
TMR5GIP
ABDOVF
ABDOVF
CSRC
CSRC
SPEN
SPEN
Bit 7
—
—
—
RCIDL
RCIDL
LCDIF
LCDIE
LCDIP
ADIE
ADIP
ADIF
Bit 6
RX9
RX9
TX9
TX9
TMR0IE
RXDTP
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
TXCKP
TXCKP
INT0IE
CREN
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SYNC
Bit 4
CTMUIF
CTMUIE
CTMUIP
SSP1IE
SSP1IP
ADDEN
ADDEN
SSP1IF
SENDB
SENDB
BRG16
BRG16
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR1GIF
TMR1GIE
TMR1GIP
TMR0IF
CCP2IE
CCP2IP
CCP2IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
 2009-2011 Microchip Technology Inc.
TMR2IF
TMR2IE
TMR2IP
CCP1IE
CCP1IP
CCP1IF
INT0IF
OERR
TRMT
OERR
TRMT
WUE
WUE
Bit 1
RTCCIE
RTCCIP
TMR1IF
TMR1IE
TMR1IP
RTCCIF
ABDEN
ABDEN
RX9D
RX9D
TX9D
TX9D
RBIF
Bit 0
on Page:
Values
Reset
75
77
77
77
77
77
77
77
77
77
79
76
77
81
82
81
81
82
82