L80227 LSI, L80227 Datasheet - Page 84

• Manufacturer Part Number: L80227
• Manufacturer: LSI

Specifications of L80227

• Lead Free Status / RoHS Status: Not Compliant

5.2 General Operation
5-2
PHYAD[4:0] address bits of the MI frame. If the states compare, the
device knows it is being addressed.
The MDA[3:0]n inputs share the same pins as the PLED[3:0]n LED
outputs, respectively. At powerup or reset, the LED output drivers are
3-stated for an interval called the power-on reset time. During the
power-on reset time, the level of these pins is latched into the device,
inverted, and used as the MI serial port physical device address.
The MI serial port is idle when at least 32 continuous 1s are detected on
the bidirectional MDIO data pin and remains idle as long as continuous
1s are detected. During idle, the MDIO output driver is in the high-
impedance state. When the MI serial port is in the idle state, a 0b01
pattern on the MDIO pin initiates a serial shift cycle. Control and address
bits are clocked into MDIO on the next 14 rising edges of MDC (the
MDIO output driver is still in a high-impedance state). If multiple register
access is not enabled, data is either shifted in or out on MDIO on the
next 16 rising edges of MDC, depending on whether a write or read cycle
was selected with the READ and WRITE operation bits. After the 32
MDC cycles have been completed
Another serial shift cycle cannot be initiated until the idle condition is
detected again (at least 32 continuous 1s).
diagram for a MI serial port cycle.
Management Interface
one complete register has been read or written
the serial shift process is halted
data is latched into the device
the MDIO output driver goes into a high-impedance state.
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure 5.1
shows a timing