L80227 LSI, L80227 Datasheet - Page 39

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L80227

Manufacturer Part Number
L80227
Description
Manufacturer
LSI
Datasheet

Specifications of L80227

Lead Free Status / RoHS Status
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2.3.9 Clock and Data Recovery
2.3.9.1 100 Mbits/s Clock and Data Recovery
2.3.9.2 10 Mbits/s Clock and Data Recovery
This section describes clock and data recovery methods implemented in
the device for both the 100 Mbits/s and 10 Mbits/s modes.
Clock recovery is accomplished with a phase-locked-loop (PLL). If valid
data is not present on the receive inputs, the PLL is locked to the 25 MHz
TX_CLK signal. When the squelch circuit detects valid data on the
receive TP input, and if the device is in the Link Pass state, the PLL input
is switched to the incoming data on the receive inputs. The PLL then
locks on to the transitions in the incoming signal to recover the clock. The
recovered data clock is then used to generate the 25 MHz RX_CLK,
which clocks data into the controller interface section.
The recovered clock extracted by the PLL latches in data from the TP
receiver to perform data recovery. The data is then converted from a
single bit stream into nibble-wide data words according to the format
shown in
The clock recovery process for 10 Mbits/s mode is identical to the 100
Mbits/s mode except
The data recovery process for 10 Mbits/s mode is identical to that of the
100 Mbits/s mode. As mentioned in the Manchester Decoder section, the
data recovery process inherently performs decoding of Manchester
encoded data from the TP inputs.
Block Diagram Description
the recovered clock frequency is a 2.5 MHz nibble clock
the PLL is switched from TX_CLK to the TP input when the squelch
indicates valid data
the PLL takes up to 12 transitions (bit times) to lock onto the
preamble, so some of the preamble data symbols are lost. However,
the clock recovery block recovers enough preamble symbols to pass
at least six nibbles of preamble to the receive controller interface as
shown in
Figure 2.3
Figure
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2.3.
2-21

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