L80227 LSI, L80227 Datasheet - Page 81

• Manufacturer Part Number: L80227
• Manufacturer: LSI

Specifications of L80227

• Lead Free Status / RoHS Status: Not Compliant

4.3.8
SPD_DET
15
7
Channel Status Output 0 Register (Register 18)
DPLX_DET
6
JAB_DIS
MREG
R
The default value for this register is 0x0000.
SPD_DET
DPLX_DET
R
Registers
5
Jabber Disable
Bit
1
0
Multiple Register Access Enable
Bit
1
0
Reserved
These bits are reserved and must remain at the default
value of 0x0 for proper device operation.
100/10 Mbits/s Speed Detect
Bit
1
0
Duplex Detect
Bit
1
0
Reserved
These bits are reserved and must remain at the default
value of 0x0 for proper device operation.
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Meaning
Device is in 100 Mbits/s mode (100BASE-TX)
Device is in 10 Mbits/s mode (10 BASE-T)
Meaning
Jabber disabled
Jabber enabled (default)
Meaning
Multiple register access enabled
No multiple register access (default)
Meaning
Device is operating in Full-Duplex
Device is operating in Half-Duplex
Reserved
Reserved
R [2:0]
R [5:0]
8
0
4-17
R 4
R 3
R 7
R 6