L80227 LSI, L80227 Datasheet - Page 29

• Manufacturer Part Number: L80227
• Manufacturer: LSI

Specifications of L80227

• Lead Free Status / RoHS Status: Not Compliant

Table 2.4
1. These 5B codes are not used. The decoder decodes these 5B codes to
Because the OSCIN input clock generates the TX_CLK output clock, the
TXD[3:0], TX_EN, and TX_ER signals are also clocked in on rising
edges of OSCIN.
On the receive side, as long as a valid data packet is not detected, CRS
and RX_DV are deasserted and the RXD[3:0] signals are held LOW.
When the start of packet is detected, CRS and RX_DV are asserted on
the falling edge of RX_CLK. The assertion of RX_DV indicates that valid
data is clocked out on RXD[3:0] on the falling edge of the RX_CLK. The
RXD[3:0] data has the same frame structure as the TXD[3:0] data and
is specified in IEEE 802.3 and shown in
packet is detected, CRS and RX_DV are deasserted, and RXD[3:0] is
held LOW. CRS and RX_DV also stay deasserted if the device is in the
Link Fail State.
RX_ER is a receive error output that is asserted when certain errors are
detected on a data nibble. RX_ER is asserted on the falling edge of
RX_CLK for the duration of that RX_CLK clock cycle during which the
nibble containing the error is output on RXD[3:0].
The collision output, COL, is asserted whenever the collision condition is
detected.
Block Diagram Description
Symbol Name
4B 0000. The encoder encodes 4B 0000 to 5B 11110, as shown in symbol
Data 0.
E
K
R
H
F
T
–
J
I
4B/5B Symbol Mapping (Cont.)
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Invalid codes
Description
SSD #1
SSD #2
ESD #1
ESD #2
Data E
Data F
Halt
Idle
Figure
All others
5B Code
0b11100
0b11101
0b11111
0b11000
0b10001
0b01101
0b00111
0b00100
2.3. When the end of the
1
Undefined
4B Code
0b0000*
0b1110
0b1111
0b0000
0b0101
0b0101
0b0000
0b0000
2-11