L80227 LSI, L80227 Datasheet - Page 28

• Manufacturer Part Number: L80227
• Manufacturer: LSI

Specifications of L80227

• Lead Free Status / RoHS Status: Not Compliant

2-10
The transmit and receive clocks operate at 25 MHz in 100 Mbits/s mode.
On the transmit side, the TX_CLK output runs continuously at 25 MHz.
When no data is to be transmitted, TX_EN must be deasserted. While
TX_EN is deasserted, TX_ER and TXD[3:0] are ignored and no data is
clocked into the device. When TX_EN is asserted on the rising edge of
TX_CLK, data on TXD[3:0] is clocked into the device on the rising edge
of the TX_CLK output clock. TXD[3:0] input data is nibble-wide packet
data whose format must be the same as specified in IEEE 802.3 and
shown in
the device, TX_EN must be deasserted on the rising edge of TX_CLK.
TX_ER is also clocked in on the rising edge of TX_CLK. TX_ER is a
transmit error signal. When this signal is asserted, the device substitutes
an error nibble in place of the normal data nibble that was clocked in on
TXD[3:0]. The error nibble is defined to be the /H/ symbol, which is
defined in IEEE 802.3 and shown in
Table 2.4
Functional Description
Symbol Name
A
B
C
D
0
1
2
3
4
5
6
7
8
9
Figure
4B/5B Symbol Mapping
2.3. When all data on TXD[3:0] has been latched into
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Description
Data C
Data D
Data A
Data B
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Table
5B Code
0b11110
0b01001
0b10100
0b10101
0b01010
0b01011
0b01110
0b01111
0b10010
0b10011
0b10110
0b10111
0b11010
0b11011
2.4.
4B Code
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101