ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 9

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

The following table captures the changes from the July 2005 issue.
The following table captures the changes from the April 2005 issue.
The following table captures the changes from the January 2005 issue.
The following table captures the changes from the November 2004 issue.
39, 40
Page
Page
Page
Page
Page
82
83
85
50
85
85
39
Section 12.6.5
Section 12.6.6
CPU_TS_ALE and CPU_TA
Section 4.5 and Section 4.6.2
Section 6.3
Figure 42
Figure 43
Section 4.6.1
Item
Item
Item
Item
Item
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Updated TXD[9:0] output delay
Updated Section 12.6.6 Management Interface Timing
(M_MDIO hold time and Figure 39)
Added mode details in Figure 40 and Figure 41
Added the CPU_TA assertion time
Added external pull-up/pull-down resistor
recommendations for SYSTEM_RST,
SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
Added Section 6.3 SYSTEM_CLK Considerations.
Clarified data sheet to indicate ZL5011x supports clock
recovery in both synchronous and asynchronous modes
of operation.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Added 5 kohm pulldown recommendation to GPIO
signals.
9
Change
Change
Change
Change
Change
Data Sheet