ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 62

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

8.9.3
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
8.9.4
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
9.0
The ZL5011x family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 4/4E
requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the
jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase
change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the
ZL5011x device operating as a master the DPLL is used to provide clock and frame reference signals to the internal
and external TDM infrastructure. In structured mode, with the ZL5011x device operating as a slave, the DPLL is not
used. All TDM clock generation is performed externally and the input streams are synchronised to the system clock
by the TDM interface. The DPLL is not required in unstructured mode, hence it is not available, because TDM
clocks and frame signals are generated by internal DCO’s assigned to each individual stream.
9.1
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown
mode.
9.1.1
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event
of a failure. These references should have the same nominal frequencies but do not need to be identical as long as
their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the
available TDM input stream clocks (up to 4 on the ZL50117/20 variants), or from the external TDM_CLKiP (primary)
or TDM_CLKiS (secondary) input pins, as illustrated in Figure 16 - on page 52. It is possible to supply a range of
input frequencies as the DPLL reference source, depicted in Table 24. The PRD register Value is the number (in
hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency
at PLL_PRI or PLL_SEC.
Input Frequency
Modes of Operation
DPLL Specification
Source
(MHz)
0.008
1.544
2.048
4.096
8.192
System Normal Mode
System Tri-state Mode
Locking Mode (normal operation)
Tolerance
(±ppm)
130
30
50
50
50
Table 24 - DPLL Input Reference Frequencies
ZL50115/16/17/18/19/20
Divider
Ratio
1
1
1
1
1
Zarlink Semiconductor Inc.
62
PRD/SRD
Register
(Note 1)
Value
(Hex)
1
1
1
1
1
Frequency at
PLL_PRI or
PLL_SEC
(MHz)
0.008
1.544
2.048
4.096
8.192
Input Wander
Acceptable
Maximum
tolerance
(Note 2)
Data Sheet
±1023
±1023
±1023
±1023
(UI)
±1