ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 52

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

6.4.3
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL5011x is capable of providing the TDM clock for either of the modes. The ZL5011x
supports clock recovery in both synchronous and asynchronous modes of operation. In asynchronous operation
each stream may have independent clock recovery.
6.4.3.1
In synchronous mode all 4 streams will be driven by a common clock source. When the ZL5011x is acting as a
master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary and
secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to the
chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the output
pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse required to
drive the TDM streams. See “DPLL Specification” on page 62 for further details.
When the ZL5011x is acting as a slave device, the common clock and frame pulse signals are taken from an
external device providing the TDM master function.
6.4.3.2
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
6.5
Data traffic received on the TDM Interface is sampled in the TDM Interface block, and synchronized to the internal
clock. It is then forwarded to the payload assembly process. The ZL5011x Payload Assembler can handle up to 128
active packet streams or “contexts” simultaneously. Each context generates a single stream of packets identified by
a label in the packet header known as the "context ID". Packet payloads are assembled in the format shown in
Figure 17 - on page 53 in structured operation. This meets the requirements of the IETF CESoPSN standard (RFC
5086). Alternatively, packet payloads are assembled in the format shown in Figure 19 - on page 55. This format
meets the requirements of the IETF SAToP standard (RFC 4553).
The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header
combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context),
which must not exceed 56 bytes.
Payload Assembly
TDM Clock Structure
TDM_CLKi[3:0]
Synchronous TDM Clock Generation
Asynchronous TDM Clock Generation
TDM_CLKiP
TDM_CLKiS
Figure 16 - Synchronous TDM Clock Generation
ZL50115/16/17/18/19/20
PRS
SRS
Zarlink Semiconductor Inc.
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PRD
SRD
DIV
DIV
Internal
DPLL
CLOCK
FRAME
PLL_PRI
PLL_SE
C
Data Sheet