ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 64

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

9.1.4
It is possible to “power down” the DPLL when it is not in use. For example, an unstructured TDM system, or use of
an external DPLL would mean the internal DPLL could be switched off, saving power. The internal registers can still
be accessed while the DPLL is powered down.
9.2
There are two identical reference monitor circuits, one for the primary and one for the secondary source. Each
circuit will continually monitor its reference, and report the references validity. The validity criteria depends on the
frequency programmed for the reference. A reference must meet all the following criteria to maintain validity:
•
•
The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the
event of an invalid signal regardless of mode.
9.3
When the reference source the DPLL is currently locking to becomes invalid, the DPLL’s response depends on
which one of the failure detect modes has been chosen: autodetect, forced primary, or forced secondary. One of
these failure detect modes must be chosen via the FDM1:0 bits of the DOM register. After a device reset via the
SYSTEM_RESET pin, the autodetect mode is selected.
In autodetect mode (automatic reference switching) if both references are valid the DPLL will synchronise to the
preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a
stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL
makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the
preferred reference using the REFSEL bit in the DOM register, after the switch to the backup reference has
occurred.
If both references are unreliable, the DPLL will drive its output clock using the stable holdover values until one of
the references becomes valid.
In forced primary mode, the DPLL will synchronise to the primary reference only. The DPLL will not switch to the
secondary reference under any circumstances including the loss of the primary reference. In this condition, the
DPLL remains in holdover mode until the primary reference recovers. Similarly in forced secondary mode, the
DPLL will synchronise to the secondary reference only, and will not switch to the primary reference. Again, a failure
of the secondary reference will cause the DPLL to enter holdover mode, until such time as the secondary reference
recovers. The choice of preferred reference has no effect in these modes.
When a conventional PLL is locked to its reference, there is no phase difference between the input reference and
the PLL output. For the DPLL, the input references can have any phase relationship between them. During a
reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The
phase jump would be transferred to the TDM outputs. The DPLL’s MTIE (Maximum Time Interval Error) feature
preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is
not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output
clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be
used.
Unlike some designs, switching between references which are at different nominal frequencies do not require
intervention such as a system reset.
The “period in specified range” check is performed regardless of the programmed frequency. Each period
must be within a range, which is programmable for the application. Refer to the ZL50115/16/17/18/19/20
Programmers Model for details.
If the programmed frequency is 1.544 MHz or 2.048 MHz, the “n periods in specified range” check will be
performed. The time taken for n cycles must be within a programmed range, typically with n at 64, the time
taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency.
Reference Monitor Circuit
Locking Mode Reference Switching
Powerdown Mode
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
64
Data Sheet