ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 31

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

4.3
For the ZL50118/19/20 variants the packet interface is capable of either 2 MII interfaces, or 1 MII and 1 GMII
interfaces, or 1 MII and 1 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an
integrated 1000BASE-X PCS module. When the packet interface is programmed for PCS/TBI mode, by default the
hardware will not enable auto-negotiation. The TBI auto-negotiation must be done by application software. The
ZL50118/19/20 supports Port 0 and Port 1.
For the ZL50115/16/17 variants the packet interface is capable of 1 MII or 1 GMII or 1 TBI (1000 Mbps) interface.
The TBI interface is a PCS interface supported by an integrated 1000BASE-X PCS module. The ZL50115/16/17
supports Port 0.
Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. Only Port 0 has the
1000 Mbps capability necessary for the GMII/TBI interface.
The ZL5011x will not take action when receiving a PAUSE frame. It will not pause the transmission of traffic. It is
normally not required to stop CESoP traffic because it is generally constant bit rate and time sensitive. If necessary,
the limiting of egress non-CESoP traffic may be done external to the ZL5011x (e.g., in an Ethernet switch).
Table 6 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 7 shows
MII Management Interface Package Ball Definition. Table 8 and Table 9 show respectively the MII Port 0 and Port 1
Interface Package Ball Definition.
All Packet Interface signals are 5 V tolerant, and all outputs are high impedance while System Reset is LOW.
Note: Mn can be either M0 or M1 for ZL5011x variants.
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_RXD[3:0]
Mn_TXD[3:0]
Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI
Packet Interfaces
Mn_RXCLK
Mn_TXCLK
Mn_RXDV
Mn_RXER
Mn_TXEN
Mn_TXER
Mn_COL
Mn_CRS
MII
-
-
-
Mn_GIGABIT_LED
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_GTX_CLK
Mn_RXD[7:0]
Mn_REFCLK
Mn_TXD[7:0]
Mn_RXCLK
Mn_RXDV
Mn_RXER
Mn_TXEN
Mn_TXER
Mn_CRS
Mn_COL
GMII
-
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
Mn_GIGABIT_LED
Mn_Signal_Detect
Mn_LINKUP_LED
Mn_ACTIVE_LED
31
Mn_GTX_CLK
Mn_REFCLK
Mn_RXD[7:0]
Mn_TXD[7:0]
Mn_RXD[8]
Mn_RXD[9]
Mn_TXD[8]
Mn_TXD[9]
Mn_RBC0
Mn_RBC1
TBI (PCS)
-
Data Sheet