ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 63

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

Note 1:
Note 2:
Note 3:
The maximum lock-in range can be programmed up to ±372 ppm regardless of the input frequency. The DPLL will
fail to lock if the source input frequency is absent, if it is not of approximately the correct frequency or if it is too
jittery. See Section 9.7 for further details. The Application Program Interface (API) software that accompanies the
ZL5011x family can be used to automatically set up the DPLL for the appropriate standard requirement.
The DPLL lock-in range can be programmed using the Lock Range register (see ZL50115/16/17/18/19/20
Programmers Model document) in order to extend or reduce the capture envelope. The DPLL provides
bit-error-free reference switching, meeting the specification limits in the Telcordia GR-1244-CORE standard. If
Stratum 4/4E accuracy is not required, it is possible to use a more relaxed system clock tolerance.
The DPLL output consists of three signals; a common clock (comclk), a double-rate common clock (comclkx2) and
a frame reference (8 kHz). These are used to time the internal TDM Interface, and hence the corresponding TDM
infrastructure attached to the interface. The output clock options are either 2.048 Mbps (comclkx2 at 4.096 Mbps)
or 8.192 Mbps (comclkx2 at 16.384 Mbps), determined by setup in the DPLL control register. The frame pulse is
programmable for polarity and width.
9.1.2
In the event of a reference failure resulting in an absence of both the primary and secondary source, the DPLL
automatically reverts to Holdover mode. The last valid frequency value recorded before failure can be maintained
within the Stratum 3 limits of ±0.05 ppm. The hold value is wholly dependent on the drift and temperature
performance of the system clock. For example, a ±32 ppm oscillator may have a temperature coefficient of
±0.1 ppm/°C. Thus a 10°C ambient change since the DPLL was last in the Locking mode will change the holdover
frequency by an additional ±1 ppm, which is much greater than the ±0.05 ppm Stratum 3 specification. If the strict
target of Stratum 3 holdover accuracy is not required, a less restrictive oscillator can be used for the system clock.
Holdover mode is typically used for a short period of time until network synchronisation is re-established.
9.1.3
In freerun mode the DPLL is programmed with a centre frequency, and can output that frequency within the
Stratum 3 limits of ±4.6 ppm. To achieve this the 100 MHz system clock must have an absolute frequency accuracy
of ±4.6 ppm. The centre frequency is programmed as a fraction of the system clock frequency.
Input Frequency
44.736 (Note 3)
Source
16.384
22.368
34.368
(MHz)
A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL.
UI means Unit Interval - in this case periods of the time signal. So ±1UI on a 64 kHz signal means ±15.625 µs, the period of
the reference frequency. Similarly ±1023UI on a 4.096 MHz signal means ±250 µs.
This input frequency is supported with the use of an external divide by 2.
6.312
Holdover Mode
Freerun Mode
Tolerance
(±ppm)
50
30
20
20
20
Table 24 - DPLL Input Reference Frequencies
ZL50115/16/17/18/19/20
Divider
Ratio
2796
537
699
1
1
Zarlink Semiconductor Inc.
63
PRD/SRD
Register
(Note 1)
Value
(Hex)
AEC
2BB
219
1
1
Frequency at
PLL_PRI or
PLL_SEC
16.384
(MHz)
6.312
0.008
0.064
0.064
±1 (on 64k Hz)
±1 (on 64 kHz)
±1 (on 64 kHz)
Input Wander
Acceptable
Maximum
tolerance
(Note 2)
Data Sheet
±1023
±1023
(UI)