ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 35

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

M1_LINKUP_LED
M1_ACTIVE_LED
M1_RXCLK
M1_COL
M1_RXD[3:0]
M1_RXDV
M1_RXER
M1_CRS
M1_TXCLK
M1_TXD[3:0]
M1_TXEN
Signal
I/O
I U
I D
I U
I D
I D
I D
I U
O
O
O
O
Table 9 - MII Port 1 Interface Package Ball Definition
C17
B15
C4
C5
[3]
[2]
D5
E4
F2
E3
[3]
[2]
A2
E1
D3
C1
B1
ZL50115/16/17/18/19/20
Package Balls
MII Port 1 (ZL50118/19/20 only)
Zarlink Semiconductor Inc.
[1]
[0]
[1]
[0]
35
D1
D2
B5
B4
LED drive for MAC 1 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
MII only - Receive Clock.
Accepts the following frequencies:
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Receive Data. Clocked on rising edge of
M1_RXCLK.
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
MII only - Transmit Clock
Accepts the following frequencies:
Transmit Data. Clocked on rising edge of
M1_TXCLK.
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
25.0 MHz
25.0 MHz
MII
MII
Description
100 Mbps
100 Mbps
Data Sheet