ZL50120GAG2 Zarlink, ZL50120GAG2 Datasheet - Page 65

• Manufacturer Part Number: ZL50120GAG2
• Description: CESoP Processors 324-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50120GAG2

• Package: 324BGA
• Maximum Data Rate: 64 Kbps
• Transmission Media Type: Copper Cables|Wireless
• Power Supply Type: Digital
• Typical Supply Current: 1.3(Max)|120(Max)|950(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3 V
• Maximum Operating Supply Voltage: 1.95|3.6 V

9.4
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is programmable up to ±372 ppm.
Note that the locking range relates to the system clock frequency. If the external oscillator has a tolerance of
-100 ppm, and the locking range is programmed to ±200 ppm, the actual locking range is the programmed value
shifted by the system clock tolerance to become -300 ppm to +100 ppm.
9.5
The Locking Time is the time it takes the synchroniser to phase lock to the input signal. Phase lock occurs when the
input and output signals are not changing in phase with respect to each other (not including jitter).
Locking time is very difficult to determine because it is affected by many factors including:
•
•
•
•
Although a short phase lock time is desirable, it is not always achievable due to other synchroniser requirements.
For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking
time; and a better (smaller) phase slope performance will increase locking time. Additionally, the locking time is
dependent on the p_shift value.
The DPLL Loop Filter and Limiter have been optimised to meet the Telcordia GR-1244-CORE jitter transfer and
phase alignment speed requirements. The phase lock time is guaranteed to be no greater than 30 seconds when
using the recommended Stratum 3 and Stratum 4/4E register settings.
9.6
The DPLL has a Lock Status Indicator and a corresponding Lock Change Interrupt. The response of the Lock
Status Indicator is a function of the programmed Lock Detect Interval (LDI) and Lock Detect Threshold (LDT) values
in the dpll_ldetect register. The LDT register can be programmed to set the jitter tolerance level of the Lock Status
Indicator. To determine if the DPLL has achieved lock the Lock Status Indicator must be high for a period of at least
30 seconds. When the DPLL loses lock the Lock Status Indicator will go low after LDI x 125 μs.
9.7
The DPLL is designed to withstand, and improve inherent jitter in the TDM clock domain.
9.7.1
For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander of up to
±1023UI
down output for T3/E3) input frequencies, the wander acceptance is limited to ±1 UI (0.1 Hz). This principle is
illustrated in Table 24.
initial input to output phase difference
initial input to output frequency difference
DPLL Loop Filter
DPLL Limiter (phase slope)
Locking Range
Locking Time
Lock Status
Jitter
pp
Acceptance of Input Wander
at 0.1 Hz to conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
65
Data Sheet