C60K-CDR-A Omron, C60K-CDR-A Datasheet - Page 34

• Manufacturer Part Number: C60K-CDR-A
• Description: PROGRAMMABLE CONTROLLER CPU
• Manufacturer: Omron

Specifications of C60K-CDR-A

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Special Relay (SR) Area
3-4-5
3-4-6
3-4-7
3-4-8
3-4-9
22
Error Flag (ER)
Step Flag
Always OFF, Always ON Flags
First Cycle Flag
Arithmetic Flags
!
!
Caution
Caution
These clock pulse bits are often used with counter instructions to create tim-
ers. Refer to 5-11 Timer and Counter Instructions for an example of this.
Because the 0.1-second clock pulse bit has an ON time of 50 ms, the CPU may
not be able to accurately read the pulses if program execution time is too long.
SR bit 1903 turns ON when the results of an arithmetic operation is not out-
put in BCD or the value of the BIN data processed by the BIN to BCD or BCD
to BIN conversion instruction exceeds 9999. When the ER flag is ON the cur-
rent instruction is not executed.
SR bit 1811 turns ON for one cycle when single-step execution is started with
the STEP instruction.
SR bits 1812 and 1814 are always OFF and 1813 is always ON. By connect-
ing these bits to external indicating devices such as a LED they can be used
to monitor the PC’s operating status.
SR bit 1815 turns ON when program execution starts and turns OFF after
one cycle.
The following flags are used in data shifting, arithmetic calculation, and com-
parison instructions. They are generally referred to only by their two-letter
abbreviations. Refer to 5-12 Data Shifting , 5-14 DAT A COMP ARE - CMP(20)
and 5-16 BCD Calculations for details.
These flags are all reset when END is executed, and therefore cannot be moni-
tored from a Programming Device.
Pulse width
Bit
.05 s
0.5 s
Bit 1900
0.1-s clock pulse
Bit 1902
1.0-s clock pulse
0.1 s
1.0 s
.05 s
0.5 s
0.1 s
1900
0.2 s
1901
1.0 s
1902
0.1 s
Bit 1901
0.2-s clock pulse
0.2 s
0.1 s
Section 3-4