C60K-CDR-A Omron, C60K-CDR-A Datasheet - Page 105

• Manufacturer Part Number: C60K-CDR-A
• Description: PROGRAMMABLE CONTROLLER CPU
• Manufacturer: Omron

Specifications of C60K-CDR-A

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer and Counter Instructions
5-11-6
94
Precautions
Flags
Limitations
HIGH-SPEED DRUM COUNTER – HDM(61)
CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the
PV is reset to zero. The PV will not be incremented or decremented while R
is ON. Counting will begin again when R goes OFF. The PV for CNTR(12)
will not be reset in interlocked program sections or for power interruptions.
Changes in II and DI execution conditions, the completion flag, and the PV
are illustrated below starting from part way through CNTR(12) operation (i.e.,
when reset, counting begins from zero). PV line height is meant to indicate
changes in the PV only.
Program execution will continue even if a non-BCD SV is used, but the SV
will not be correct.
ER:
If any of the lower limits for the DM ranges are set to “0000,” the correspond-
ing output bits are turned ON when the high-speed counter is reset.
If the time it takes to count through some range is less than the cycle time of
the CPU, the high-speed counter may count past between cycles and thus
the output bit for this range may not be turned ON.
The count signal must be at least 250 s (2 kHz) wide and have a duty factor
of 1:1, as shown below.
Execution condition
on increment (II)
Execution condition
on decrement (DI)
Completion flag
PV
Ladder Symbol
SV is not in BCD.
Input
0000
HDM(61) N
Lower Limit
250 S
R
ON
OFF
ON
OFF
ON
OFF
250 S
SV - 2
SV - 1
Counting
Time
SV
0000
Operand Data Areas
Definer Values
R: Result word
0001
N: TC number
IR, HR, DM
Must be 47
Upper Limit
0000
Section 5-11
SV
SV - 1
SV - 2