C60K-CDR-A Omron, C60K-CDR-A Datasheet - Page 121

• Manufacturer Part Number: C60K-CDR-A
• Description: PROGRAMMABLE CONTROLLER CPU
• Manufacturer: Omron

Specifications of C60K-CDR-A

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Data Shifting
Flags
5-12-3
110
Description
Limitations
WORD SHIFT – WSFT(16)
!
Caution
SFTR(84) is used to create a single- or multiple-word shift register that can
be shifted to either the right or the left. To create a single-word shift register,
designate the same word for St and E. The control word provides the shift
direction, the status to be input into the register, the shift pulse, and the reset
input. The control word is allocated as follows:
The data in the shift register will be shifted one bit in the direction indicated
by bit 12, shifting one bit out to CY and the status of bit 13 into the other end
whenever SFTR(84) is executed with an ON execution condition as long as
the reset bit is OFF and as long as bit 14 is ON. If SFTR(84) is executed with
an OFF execution condition or if SFTR(84) is executed with bit 14 OFF, the
shift register will remain unchanged. If SFTR(84) is executed with an ON ex-
ecution condition and the reset bit (bit 15) is OFF, the entire shift register and
CY will be set to zero.
ER:
CY
If the execution condition for SFTR(84) is ON and bit 14 is ON, the status of bit 13
will be shifted into the register every cycle. Use DIFU(13) or DIFD(14) when it is
necessary to ensure that the shift is made only once each time the execution
condition comes ON.
St and E must be in the same data area and St must be less than E.
Ladder Symbols
St and E are not in the same data area or St is greater than E.
Indirectly addressed DM word is non-existent. (Content of DM word
is not BCD, or the DM area boundary has been exceeded.)
Receives the status of bit 00 of St or bit 15 of E depending on the
shift direction.
15 14 13 12
WSFT(16)
St
E
Not used.
Operand Data Areas
Shift direction
1 (ON):
0 ()FF:
Status to input into register
Shift pulse bit
Reset
St : Start word
E : End word
IR, DM, HR
IR, DM, HR
Left
Right
Section 5-12