PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC18LF8490-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8490-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F6390/6490/8390/8490
TABLE 5-2:
DS39629C-page 78
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.
EUSART1 Transmit Register
PORTD Data Direction Register
PORTC Data Direction Register
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
PORTJ Data Direction Register
PORTH Data Direction Register
PORTF Data Direction Register
PORTE Data Direction Register
PORTB Data Direction Register
LATJ Data Output Register
LATH Data Output Register
LATF Data Output Register
LATE Data Output Register
LATD Data Output Register
LATC Data Output Register
LATB Data Output Register
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
TRISA7
LATA7
OSCFIP
OSCFIE
INTSRC
OSCFIF
CSRC
RA7
SPEN
Bit 7
—
—
—
—
—
—
—
—
—
PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
(5)
(5)
(5)
TRISA6
PLLEN
LATA6
LCDIP
LCDIE
RA6
LCDIF
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
RX9
TX9
—
—
—
(5)
(5)
(3)
(5)
PORTA Data Direction Register
LATA Data Output Register
Read PORTA pins, Write PORTA Data Latch
RC2IP
RC2IE
RC1IP
RC1IE
RG5
SREN
RC2IF
RC1IF
TXEN
Bit 5
—
—
—
—
—
—
(4)
PORTG Data Direction Register
LATG Data Output Register
Read PORTG pins <4:0>, Write PORTG Data Latch <4:0>
CREN
SYNC
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
TUN4
Bit 4
—
—
—
SENDB
ADDEN
BCLIP
BCLIE
SSPIP
SSPIF
SSPIE
BCLIF
TUN3
Bit 3
—
—
—
—
—
—
CCP1IP
CCP1IE
HLVDIP
HLVDIF
HLVDIE
CCP1IF
BRGH
FERR
TUN2
Bit 2
—
—
—
—
—
—
TMR3IP
TMR3IE
TMR2IP
TMR2IE
TMR3IF
TMR2IF
OERR
TRMT
TUN1
Bit 1
—
—
—
—
—
—
© 2007 Microchip Technology Inc.
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TX9D
RX9D
TUN0
Bit 0
—
—
—
—
—
—
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
-111 ----
-000 ----
-000 ----
11-- 1111
00-- 0000
00-- 0000
-111 1111
-000 0000
-000 0000
00-0 0000
1111 1111
1111 1111
---1 1111
1111 1111
1111 ----
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
xxxx ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
POR, BOR
Value on
on page:
Details
61, 201
61, 208
61, 206
61, 198
61, 199
61, 106
61, 100
61, 103
61, 105
61, 102
61, 104
61, 101
62, 130
62, 128
62, 126
62, 124
62, 121
62, 119
62, 117
62, 114
62, 130
62, 128
62, 126
62, 124
62, 121
62, 119
62, 117
62, 114
62, 130
62, 128
62, 126
62, 124
62, 121
62, 119
62, 117
62, 114
62, 111
62, 111
62, 111
61, 99
61, 98
35, 61