PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet - Page 409

• Manufacturer Part Number: PIC18LF8490-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8490-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

© 2007 Microchip Technology Inc.
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 372
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision for Transmit and Acknowledge ........... 191
Capture/Compare/PWM (All CCP Modules) ............ 374
CLKO and I/O .......................................................... 371
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 69
Example SPI Master Mode (CKE = 0) ..................... 375
Example SPI Master Mode (CKE = 1) ..................... 376
Example SPI Slave Mode (CKE = 0) ....................... 377
Example SPI Slave Mode (CKE = 1) ....................... 378
External Clock (All Modes Except PLL) ................... 369
Fail-Safe Clock Monitor ............................................ 291
High/Low-Voltage Detect Characteristics ................ 366
High-Voltage Detect Operation (VDIRMAG = 1) ...... 254
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD Interrupt Timing in Quarter-Duty Cycle Drive ... 276
LCD Sleep Entry/Exit When SLPEN = 1 or
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 253
Master SSP I
Master SSP I
PWM Output ............................................................ 153
Repeat Start Condition ............................................. 186
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 211
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 162
SPI Mode (Slave Mode, CKE = 0) ........................... 164
SPI Mode (Slave Mode, CKE = 1) ........................... 164
Synchronous Reception
Synchronous Transmission .............................. 212, 226
Synchronous Transmission
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 379
C Bus Start/Stop Bits ............................................. 379
C Master Mode (7 or 10-Bit Transmission) ........... 188
C Master Mode (7-Bit Reception) .......................... 189
C Master Mode First Start Bit ................................ 185
C Slave Mode (10-Bit Reception, SEN = 0) .......... 174
C Slave Mode (10-Bit Reception, SEN = 1) .......... 179
C Slave Mode (10-Bit Transmission) ..................... 175
C Slave Mode (7-Bit Reception, SEN = 0) ............ 172
C Slave Mode (7-Bit Reception, SEN = 1) ............ 178
C Slave Mode (7-Bit Transmission) ....................... 173
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 190
During Start Condition ..................................... 193
Start Condition (Case 1) .................................. 194
Start Condition (Case 2) .................................. 194
Condition (SCL = 0) ......................................... 193
Condition (SDA Only) ...................................... 192
Condition (Case 1) ........................................... 195
Condition (Case 2) ........................................... 195
Sequence (7 or 10-Bit Addressing Mode) ........ 180
CS1:CS0 = 00 .................................................. 277
Timer (OST) and Power-up Timer (PWRT) ..... 372
V
(Master Mode, SREN) ............................. 214, 228
(Through TXEN) ...................................... 213, 227
DD
Rise > T
2
2
C Bus Data ........................................ 381
C Bus Start/Stop Bits ........................ 381
PWRT
) ............................................ 57
DD
,
PIC18F6390/6490/8390/8490
Timing Diagrams and Specifications
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 373
Transition for Entry to PRI_IDLE Mode ..................... 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) .................. 45
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 44
Type-A in 1/2 MUX, 1/2 Bias Drive .......................... 266
Type-A in 1/2 MUX, 1/3 Bias Drive .......................... 268
Type-A in 1/3 MUX, 1/2 Bias Drive .......................... 270
Type-A in 1/3 MUX, 1/3 Bias Drive .......................... 272
Type-A in 1/4 MUX, 1/3 Bias Drive .......................... 274
Type-A/Type-B in Static Drive ................................. 265
Type-B in 1/2 MUX, 1/2 Bias Drive .......................... 267
Type-B in 1/2 MUX, 1/3 Bias Drive .......................... 269
Type-B in 1/3 MUX, 1/2 Bias Drive .......................... 271
Type-B in 1/3 MUX, 1/3 Bias Drive .......................... 273
Type-B in 1/4 MUX, 1/3 Bias Drive .......................... 275
USART Synchronous Receive (Master/Slave) ........ 383
USART Synchronous Transmission
A/D Conversion Requirements ................................ 385
AC Characteristics - Internal RC Accuracy .............. 370
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 371
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 369
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 370
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
USART Synchronous Receive
USART Synchronous Transmission
2
2
C Bus Data Requirements (Slave Mode) .............. 380
C Bus Start/Stop Bits Requirements
(MCLR Tied to V
MCLR Not Tied to V
MCLR Not Tied to V
MCLR Tied to V
(INTOSC to HSPLL) ........................................ 289
PRI_RUN Mode ................................................. 44
PRI_RUN Mode (HSPLL) .................................. 43
(Master/Slave) ................................................. 383
(All CCP Modules) ........................................... 374
(Master Mode, CKE = 0) .................................. 375
(Master Mode, CKE = 1) .................................. 376
(Slave Mode, CKE = 0) .................................... 377
(CKE = 1) ......................................................... 378
(Slave Mode) ................................................... 379
Requirements .................................................. 381
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 372
Clock Requirements ........................................ 373
Requirements .................................................. 383
Requirements .................................................. 383
2
2
C Bus Data Requirements ................ 382
C Bus Start/Stop Bits
DD
DD
, V
) .......................................... 57
DD
DD
DD
, Case 1 ......................... 56
, Case 2 ......................... 56
Rise < T
DS39629C-page 407
PWRT
............. 56