PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet - Page 203

• Manufacturer Part Number: PIC18LF8490-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8490-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.1
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
The SPBRGH1:SPBRG1 register pair controls the period
of a free-running timer. In Asynchronous mode, the
BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 16-1 shows the formula for computation
of the baud rate for different EUSART modes that only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 16-1. From
this, the error in baud rate can be determined. An exam-
ple calculation is shown in Example 16-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 16-3. It may be advanta-
TABLE 16-1:
EXAMPLE 16-1:
TABLE 16-2:
© 2007 Microchip Technology Inc.
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
TXSTA1
RCSTA1
BAUDCON1
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRGH1:SPBRG1:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
SYNC
Name
0
0
0
0
1
1
EUSART Baud Rate Generator
(BRG)
Configuration Bits
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
ABDOVF
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
BRG16
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
OSC
X = ((F
0
0
1
1
0
1
CALCULATING BAUD RATE ERROR
= F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
RCIDL
OSC
Bit 6
RX9
TX9
OSC
/(64 ([SPBRGH1:SPBRG1] + 1))
BRGH
/Desired Baud Rate)/64) – 1
0
1
0
1
x
x
OSC
SREN
TXEN
Bit 5
—
, the nearest
PIC18F6390/6490/8390/8490
SYNC
CREN
SCKP
Bit 4
BRG/EUSART Mode
16-Bit/Asynchronous
16-Bit/Asynchronous
16-Bit/Synchronous
8-Bit/Asynchronous
8-Bit/Asynchronous
8-Bit/Synchronous
SENDB
ADDEN
BRG16
Bit 3
geous to use the high baud rate (BRGH = 1) or the 16-bit
BRG to reduce the baud rate error, or achieve a slow
baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH1:SPBRG1 regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
16.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
16.1.2
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX1 pin.
BRGH
FERR
Bit 2
—
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
WUE
Bit 1
Baud Rate Formula
F
F
ABDEN
F
RX9D
OSC
OSC
TX9D
Bit 0
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39629C-page 201
Reset Values
on Page
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