PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet - Page 128

• Manufacturer Part Number: PIC18LF8490-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8490-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F6390/6490/8390/8490
TABLE 9-14:
TABLE 9-15:
DS39629C-page 126
RG0/SEG30
RG1/TX2/CK2/
SEG29
RG2/RX2/DT2/
SEG28
RG3/SEG27
RG4/SEG26
MCLR/V
Legend:
Note 1:
PORTG
LATG
TRISG
LCDSE3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
Pin Name
Name
PP
/RG5
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RG5 does not have a corresponding TRISG bit.
RG5 is available as an input only when MCLR is disabled.
SE31
Bit 7
—
—
—
Function
PORTG FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
SEG30
SEG29
SEG28
SEG27
SEG26
MCLR
RG0
RG1
CK2
RG2
RX2
DT2
RG3
RG4
RG5
TX2
V
PP
SE30
Bit 6
—
—
—
Setting
TRIS
—
—
—
0
1
x
0
1
1
1
1
x
0
1
1
1
1
x
0
1
0
0
1
x
(1)
(1)
(1)
RG5
SE29
Bit 5
I/O
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
(1)
Buffer
ANA
ANA
ANA
ANA
ANA
ANA
Read PORTG pin/Write PORTG Data Latch
LATG Data Output Register
PORTG Data Direction Register
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
SE28
Bit 4
LATG<0> data output; disabled when LCD segment enabled.
PORTG<0> data input.
Segment 30 analog output for LCD.
LATG<1> data output; disabled when LCD segment enabled.
PORTG<1> data input.
Synchronous serial data output (AUSART module); takes priority over
port data.
Synchronous serial data input (AUSART module). User must configure
as an input.
Synchronous serial clock input (AUSART module).
Segment 29 analog output for LCD.
LATG<2> data output; disabled when LCD segment enabled.
PORTG<2> data input.
Asynchronous serial receive data input (AUSART module).
Synchronous serial data output (AUSART module); takes priority over
port data.
Synchronous serial data input (AUSART module). User must configure
as an input.
Segment 28 analog output for LCD.
LATG<3> data output; disabled when LCD segment enabled.
PORTG<3> data input.
Segment 27 analog output for LCD.
LATG<4> data output; disabled when LCD segment enabled.
PORTG<4> data input.
Segment 26 analog output for LCD.
External Master Clear input; enabled when MCLRE Configuration bit is set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTG<5> data input; enabled when MCLRE Configuration bit is clear.
SE27
Bit 3
SE26
Bit 2
Description
SE25
Bit 1
© 2007 Microchip Technology Inc.
SE24
Bit 0
Reset Values
on Page
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