PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet
PIC18LF8490-I/PT
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... PIC18F6390/6490/8390/8490 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology © 2007 Microchip Technology Inc. Data Sheet DS39629C ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F8390 8K 4096 768 PIC18F8490 16K 8192 768 © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Four External Interrupts • Four Input Change Interrupts • Four 8-Bit/16-Bit Timer/Counter modules • Real-Time Clock (RTC) Software module: - Configurable 24-hour clock, calendar, automatic ...
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... PP 7 RG4/SEG26 RF7/SS/SEG25 11 RF6/AN11/SEG24 12 RF5/AN10/CV /SEG23 REF 13 RF4/AN9/SEG22 14 RF3/AN8/SEG21 15 RF2/AN7/C1OUT/SEG20 16 Note 1: RE7 is the alternate pin for CCP2 multiplexing DS39629C-page PIC18F6390 PIC18F6490 RB0/INT0 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9 46 RB3/INT3/SEG10 45 RB4/KBI0/SEG11 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO/SEG12 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1/SEG13 © 2007 Microchip Technology Inc. ...
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... RG3/SEG27 8 MCLR/V /RG5 PP 9 RG4/SEG26 RF7/SS/SEG25 13 RF6/AN11/SEG24 14 RF5/AN10/CV /SEG23 REF 15 RF4/AN9/SEG22 16 RF3/AN8/SEG21 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: RE7 is the alternate pin for CCP2 multiplexing © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 PIC18F8390 PIC18F8490 RJ2/SEG34 60 RJ3/SEG35 59 RB0/INT0 58 RB1/INT1/SEG8 57 RB2/INT2/SEG9 56 RB3/INT3/SEG10 55 RB4/KBI0/SEG11 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 ...
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... Appendix E: migration from Mid-Range to Enhanced Devices .......................................................................................................... 397 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 397 Index .................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 409 Customer Change Notification Service .............................................................................................................................................. 409 Customer Support .............................................................................................................................................................................. 409 Reader Response .............................................................................................................................................................................. 410 PIC18F6390/6490/8390/8490 Product Identification System ............................................................................................................ 411 DS39629C-page 4 © 2007 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 DS39629C-page 5 ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 6 © 2007 Microchip Technology Inc. ...
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... Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced 80%, with typical values of 1.1 μA and 2.1 μA, respectively. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F6390/6490/8390/8490 ...
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... Standard devices with Flash memory, designated with an “F” in the part number (such as PIC18F6390), accommodate an operating V range of 4.2V to 5.5V. Low-voltage DD parts, designated by “LF” (such as PIC18LF6490), function over an extended V range of 2.0V to 5.5V. DD © 2007 Microchip Technology Inc. and 80-pin Kbytes for ...
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... Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) RESET Instruction, Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 83 with Extended Packages © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 PIC18F6390 PIC18F6490 DC – 40 MHz DC – 40 MHz 8K 16K 4096 ...
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... RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 RC6/TX1/CK1 RC7/RX1/DT1 PORTD RD7/SEG7:RD0/SEG0 PORTE LCDBIAS1 LCDBIAS2 LCDBIAS3 COM0 RE4/COM1 RE5/COM2 RE6/COM3 (1) RE7/CCP2 /SEG31 PORTF RF0/AN5/SEG18 RF1/AN6/C2OUT/SEG19 RF2/AN7/C1OUT/SEG20 RF3/AN8/SEG21 RF4/AN9/SEG22 RF5/AN10/CV /SEG23 REF RF6/AN11/SEG24 RF7/SS/SEG25 PORTG RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 RG4/SEG26 (2) MCLR/V /RG5 PP © 2007 Microchip Technology Inc. ...
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... RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Data Bus<8> Data Latch ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. O Analog SEG5 output for LCD. I/O ST Digital I/O. O Analog SEG6 output for LCD. I/O ST Digital I/O. O Analog SEG7 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTE is a bidirectional I/O port. I Analog BIAS1 input for LCD ...
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... Analog Analog input 11. O Analog SEG24 output for LCD. I/O ST Digital I/O. I TTL SPI slave select input. O Analog SEG25 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. O Analog SEG5 output for LCD. I/O ST Digital I/O. O Analog SEG6 output for LCD. I/O ST Digital I/O. O Analog SEG7 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTE is a bidirectional I/O port. I Analog BIAS1 input for LCD ...
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... Analog Analog input 11. O Analog SEG24 output for LCD. I/O ST Digital I/O. I TTL SPI slave select input. O Analog SEG25 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. O Analog SEG41 output for LCD. I/O ST Digital I/O. O Analog SEG42 output for LCD. I/O ST Digital I/O. O Analog SEG43 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2007 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Pin Buffer Type Type PORTJ is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 30 © 2007 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... FIGURE 2-4: of external Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2007 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator ...
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... Three discussed in Section 2.6.5.1 “Compensating with the AUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the Timers”, but other techniques may be used. or temperature changes, which can compensation techniques are © 2007 Microchip Technology Inc. ...
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... Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register ...
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... MHz 101 1 MHz 100 500 kHz 011 250 kHz FOSC3:FOSC0 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> © 2007 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... INTRC is providing the clock, or the internal oscillator block has just started and is not yet stable. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see Section 2.6.3 “OSCTUNE Register”. 3: Default output frequency of INTOSC on Reset. DS39629C-page 38 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... LP, XT and HS Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 40 © 2007 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock provides the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. © 2007 Microchip Technology Inc. ...
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... FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 OST OSC PLL © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 n-1 n Clock Transition OST (1) PLL ( n-1 Clock ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) OST T PLL 1 2 n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale © 2007 Microchip Technology Inc. ...
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... Wake Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 3.4 Idle Modes in the The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8 CSD PC is CSD © 2007 Microchip Technology Inc. ...
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... In such situations, initial oscillator operation is far from stable and unpredictable operation may result. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer ...
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... EC and INTIO Oscillator modes). However, a fixed delay of interval following the wake event, is still required when CSD leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2007 Microchip Technology Inc. ...
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... Section 3.4 “Idle Modes”). 3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies the Oscillator Start-up Timer (parameter 32). t OST also designated PLL 5: Execution continues during T © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Clock Source Exit Delay after Wake-up LP, XT, HS HSPLL T CSD (1) EC, RC, INTRC (3) ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 50 © 2007 Microchip Technology Inc. ...
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... INTRC 11-Bit Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39629C-page 52 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 FIGURE 4-2: V ...
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... BOR is disabled; must be enabled by reprogramming the Configuration bits. BOR is enabled in software; operation controlled by SBOREN. BOR is enabled in hardware and active during the Run and Idle modes, disabled during Sleep mode. BOR is enabled in hardware; must be disabled by reprogramming the Configuration bits. © 2007 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39629C-page PWRT T OST T PWRT T OST T PWRT T OST © 2007 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 , V RISE > PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (1) ( (1) ( STKPTR Register POR BOR STKFUL STKUNF © 2007 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: These registers are cleared on POR and unchanged on BOR. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: These registers are cleared on POR and unchanged on BOR. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 MCLR Resets Power-on Reset, ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: These registers are cleared on POR and unchanged on BOR. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 MCLR Resets Power-on Reset, ...
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... Wake-up via WDT or Interrupt (6) uuuu uuuu (6) uuuu uuuu (6) uuuu uuuu (6) uuuu uuuu (6) uuuu uuuu (6) uuuu uuuu uuu- uuuu uuuu uuuu © 2007 Microchip Technology Inc. ...
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... On-Chip Program Memory 1FFFh 2000h Read ‘0’ 1FFFFFh © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 A set of three registers, Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch register (TABLAT) contains the data that is read from the program memory. Data is transferred from program memory one byte at a time. Table read operation is discussed Section 6.1 “Table Reads”. © 2007 Microchip Technology Inc. nn further in ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 5.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Data Memory 000h 7 ...
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... LATC (2) — F8Ah LATB (2) — F89h LATA (2) (3) — F88h PORTJ (2) (3) — F87h PORTH (2) — F86h PORTG IPR3 F85h PORTF PIR3 F84h PORTE PIE3 F83h PORTD IPR2 F82h PORTC PIR2 F81h PORTB PIE2 F80h PORTA © 2007 Microchip Technology Inc. ...
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... F70h LCDDATA11 Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 64-pin devices. 4: This register is implemented but unused on 64-pin devices. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Name Address F6Fh SPBRG2 F5Fh LCDSE5 F6Eh RCREG2 F5Eh ...
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... N/A 59, 82 N/A 59, 83 N/A 59, 83 N/A 59, 83 N/A 59, 83 60, 82 ---- xxxx 60, 82 xxxx xxxx 60, 71 ---- 0000 N/A 60, 82 N/A 60, 83 N/A 60, 83 N/A 60, 83 N/A 60, 83 60, 82 ---- xxxx 60, 82 xxxx xxxx DC C 60, 80 ---x xxxx © 2007 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 ...
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... Table 24-2 and Table 24-3. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Purpose Register File”), or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘ ...
Page 84
... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2007 Microchip Technology Inc. ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
Page 86
... Figure 5-8. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 24.2.1 “Extended Instruction Syntax”. © 2007 Microchip Technology Inc. ...
Page 87
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 000h 060h Bank 0 100h Bank 1 through ...
Page 88
... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2007 Microchip Technology Inc. ...
Page 89
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Table reads work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address ...
Page 90
... TABLAT. A typical method for reading data from program memory is shown in Example 6-1. Program Memory (Odd Byte Address) TBLPTR = xxxxx1 TBLRD TABLE POINTER OPERATIONS WITH TBLRD INSTRUCTIONS Operation on Table Pointer TBLPTR = xxxxx0 TABLAT Read Register © 2007 Microchip Technology Inc. ...
Page 91
... Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 90 © 2007 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 EXAMPLE 7-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 7-2: MOVF ARG1, W MULWF ARG2 ...
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... MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; © 2007 Microchip Technology Inc. ...
Page 95
... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices ...
Page 96
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2007 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
Page 97
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note: Interrupt flag bits are set when an interrupt ...
Page 98
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39629C-page 96 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-0 ...
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... R-0 R/W-0 R/W-0 TX1IF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 U-0 R/W-0 R/W-0 — BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 102
... The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written The AUSART transmit buffer is full bit 3-0 Unimplemented: Read as ‘0’ DS39629C-page 100 R/W-0 U-0 U-0 TX2IF — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-0 R/W-0 R/W-0 TX1IE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39629C-page 102 U-0 R/W-0 R/W-0 — BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
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... RC2IE: AUSART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: AUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R-0 U-0 U-0 TX2IE — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39629C-page 104 R/W-1 R/W-1 R/W-1 TX1IP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 U-0 R/W-1 R/W-1 — BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 108
... TX2IP: AUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3-0 Unimplemented: Read as ‘0’ DS39629C-page 106 R/W-1 U-0 U-0 TX2IP — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 110
... Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2007 Microchip Technology Inc. ...
Page 111
... PORT Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 9.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
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... Main clock input connection, all modes except INTIO. O DIG LATA<7> data output. Available only in INTIO modes; otherwise reads as ‘0’. I TTL PORTA<7> data input. Available only in INTIO modes; otherwise reads as ‘0’. Description /4) in all oscillator modes except OSC © 2007 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 ...
Page 114
... Polling of PORTB is not recommended while using the interrupt-on-change feature. RB4:RB1 are also multiplexed with LCD segment drives controlled by bits in the LCDSE1 register. I/O port functions are only available when the segments are disabled. © 2007 Microchip Technology Inc. device from ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: All other pin functions are disabled when ICSP or ICD are enabled. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 I/O Buffer ...
Page 116
... DS39629C-page 114 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF SE13 SE12 SE11 SE10 Reset Bit 1 Bit 0 Values on Page RB1 RB0 INT0IF RBIF 59 INT3IP RBIP 59 INT2IF INT1IF 59 SE9 SE8 64 © 2007 Microchip Technology Inc. ...
Page 117
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note Power-on Reset, these pins are configured as digital inputs ...
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... LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (EUSART module). O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Description © 2007 Microchip Technology Inc. ...
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... Bit 6 PORTC RC7 RC6 LATC LATC Data Output Register TRISC PORTC Data Direction Register LCDSE1 SE15 SE14 Legend: Shaded cells are not used by PORTC. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 SE13 SE12 SE11 ...
Page 120
... PORTD<7> data input. O ANA Segment 7 analog output for LCD. INITIALIZING PORTD ; Initialize PORTD by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Description © 2007 Microchip Technology Inc. ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD Data Output Register TRISD PORTD Data Direction Register LCDSE0 SE7 SE6 © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 SE5 SE4 SE3 SE2 ...
Page 122
... PORTE Available for I/O RE6, RE5, RE4 RE6, RE5 RE6 None INITIALIZING PORTE ; Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE<5:4> as inputs ; RE<7:6> as outputs © 2007 Microchip Technology Inc. ...
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... PORTE Data Direction Register LCDCON LCDEN SLPEN LCDSE3 SE31 SE30 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Buffer DIG LATE<4> data output; disabled when LCD common enabled. ST PORTE<4> data input. ANA Common 1 analog output for LCD ...
Page 124
... MOVLW 0x07 ; MOVWF CMCON ; Turn off comparators MOVLW 0x0F ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF0 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs © 2007 Microchip Technology Inc. ...
Page 125
... SEG25 x Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 I/O Buffer O DIG LATF< ...
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... VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 CVRR CVRSS CVR3 CVR2 SE21 SE20 SE19 SE18 SE29 SE28 SE27 SE26 Reset Values Bit 1 Bit 0 on Page PCFG1 PCFG0 61 CM1 CM0 61 CVR1 CVR0 61 SE17 SE16 64 SE25 SE24 64 © 2007 Microchip Technology Inc. ...
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... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 PORTG<4:0> are also multiplexed with LCD segment drives controlled by bits in the LCDSE3 register. I/O port functions are only available when the segments are disabled ...
Page 128
... PORTG<5> data input; enabled when MCLRE Configuration bit is clear. Bit 5 Bit 4 Bit 3 Bit 2 (1) Read PORTG pin/Write PORTG Data Latch — LATG Data Output Register — PORTG Data Direction Register SE28 SE27 SE26 Description Reset Values Bit 1 Bit 0 on Page SE25 SE24 64 © 2007 Microchip Technology Inc. ...
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... On a Power-on Reset, these pins are configured as digital inputs. PORTH is also multiplexed with LCD segment drives controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 EXAMPLE 9-8: CLRF PORTH ...
Page 130
... Segment 42 analog output for LCD. O DIG LATH<7> data output; disabled when LCD segment enabled PORTH<7> data input. O ANA Segment 43 analog output for LCD. Bit 5 Bit 4 Bit 3 Bit 2 SE45 SE44 SE43 SE42 Description Reset Values Bit 1 Bit 0 on Page SE41 SE40 64 © 2007 Microchip Technology Inc. ...
Page 131
... On a Power-on Reset, these pins are configured as digital inputs. PORTJ is also multiplexed with LCD segment drives controlled by the LCDSE4 register. I/O port functions are only available when the segments are disabled. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 EXAMPLE 9-9: CLRF PORTJ ...
Page 132
... Segment 37 analog output for LCD. O DIG LATJ<7> data output; disabled when LCD segment enabled PORTJ<7> data input. O ANA Segment 36 analog output for LCD. Bit 5 Bit 4 Bit 3 Bit 2 SE36 SE35 SE34 Description Reset Values Bit 1 Bit 0 on Page SE33 SE32 64 © 2007 Microchip Technology Inc. ...
Page 133
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1 ...
Page 134
... Sync with TMR0L Internal Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 135
... GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT TRISA PORTA Data Direction Register Legend: Shaded cells are not used by Timer0. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 134 © 2007 Microchip Technology Inc. ...
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... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... Special Event Trigger) 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 139
... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 140
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. a Special Event Trigger © 2007 Microchip Technology Inc. ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 142
... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 140 © 2007 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 144
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSPIF CCP1IF TX1IE SSPIE CCP1IE TX1IP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 59 TMR2IF TMR1IF 61 TMR2IE TMR1IE 61 TMR2IP TMR1IP © 2007 Microchip Technology Inc. ...
Page 145
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 A simplified block diagram of the Timer3 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The Timer3 module is controlled through the T3CON register (Register 13-1) ...
Page 146
... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 TMR3H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 147
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 13.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 148
... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 146 © 2007 Microchip Technology Inc. ...
Page 149
... PWM mode Note 1: CCPxM3:CCPxM0 = 1011 will only reset the timer and not start the A/D conversion on the CCPx match. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register ...
Page 150
... TMR1 TMR3 CCP1 CCP2 TMR2 Timer3 is used for all capture and compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. © 2007 Microchip Technology Inc. ...
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... Capture PWM* None Compare PWM* None PWM* Capture None PWM* Compare None PWM* PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). * Includes standard and Enhanced PWM operation. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Interaction DS39629C-page 149 ...
Page 152
... CAPTURE PRESCALERS ; Turn CCP module off ; new prescaler mode ; value and CCP ON ; Load CCP2CON with ; this value TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L © 2007 Microchip Technology Inc. ...
Page 153
... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 14.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M3:CCP2M0 = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated if enabled and the CCP2IE bit is set. ...
Page 154
... DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 59 PD POR BOR 60 TMR2IF TMR1IF 61 TMR2IE TMR1IE 61 TMR2IP TMR1IP 61 TMR3IF CCP2IF 61 TMR3IE CCP2IE 61 TMR3IP CCP2IP 61 62 — — — TMR1CS TMR1ON TMR3CS TMR3ON © 2007 Microchip Technology Inc. ...
Page 155
... Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 A PWM output (Figure 14-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
Page 156
... If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be cleared. 9.77 kHz 39.06 kHz FFh FFh ⎛ ⎞ OSC log --------------- ⎝ ⎠ F PWM = -----------------------------bits log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2007 Microchip Technology Inc. ...
Page 157
... CCPR2H Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
Page 158
... PIC18F6390/6490/8390/8490 NOTES: DS39629C-page 156 © 2007 Microchip Technology Inc. ...
Page 159
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
Page 160
... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R bit Bit is unknown ...
Page 161
... In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as inputs or outputs. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 R/W-0 R/W-0 (2) (3) ...
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... Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. © 2007 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.3.4 TYPICAL CONNECTION Figure 15-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
Page 164
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 165
... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39629C-page 164 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 2 bit 5 bit 4 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
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... WCOL SSPOV SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 15.3.10 ...
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... SSPBUF and the SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. © 2007 Microchip Technology Inc. ...
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... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2 C™ MODE) ...
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... C™ MODE) R/W-0 R/W-0 (1) (2) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /(4 * (SSPADD + 1)) OSC R/W-0 R/W-0 R/W-0 (2) (2) (2) SSPM1 SSPM0 bit Bit is unknown 2 C conditions were not valid for a © 2007 Microchip Technology Inc. ...
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... Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 2 C™ MODE) R/W-0 R/W-0 ...
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... Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (SSPIF and BF bits are set). 9. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. © 2007 Microchip Technology Inc. ...
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... The clock must be released by setting bit CKP (SSPCON1<4>). See Section 15.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39629C-page 172 © 2007 Microchip Technology Inc. ...
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... FIGURE 15-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 DS39629C-page 173 ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39629C-page 174 © 2007 Microchip Technology Inc. ...
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... FIGURE 15-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 DS39629C-page 175 ...
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... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 15-11). © 2007 Microchip Technology Inc. ...
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... SDA DX SCL CKP WR SSPCON © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 15-12) ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39629C-page 178 © 2007 Microchip Technology Inc. ...
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... FIGURE 15-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 DS39629C-page 179 ...
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... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 15-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ © 2007 Microchip Technology Inc. ...
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... Generate a Stop condition on SDA and SCL. FIGURE 15-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 184
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2007 Microchip Technology Inc. ...
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... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 186
... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2007 Microchip Technology Inc. ...
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... FIGURE 15-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG 1st bit Write to SSPBUF occurs here T BRG Sr = Repeated Start T BRG © 2007 Microchip Technology Inc. ...
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... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC18F6390/6490/8390/8490 2 FIGURE 15-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39629C-page 188 © 2007 Microchip Technology Inc. ...
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... FIGURE 15-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 DS39629C-page 189 ...
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... PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2007 Microchip Technology Inc. ...
Page 193
... FIGURE 15-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 15.4.17 MULTI-MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software © 2007 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG © 2007 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...
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... SCL PEN BCLIF P SSPIF © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> ...
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... C Slave Mode. MSSP Baud Rate Reload Register in I SSPEN CKP SSPM3 SSPM2 ACKDT ACKEN RCEN PEN D R/W Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 59 TMR2IF TMR1IF 61 TMR2IE TMR1IE 61 TMR2IP TMR1IP Slave Mode. 60 SSPM1 SSPM0 60 RSEN SEN © 2007 Microchip Technology Inc. ...
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... Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity © 2007 Microchip Technology Inc. PIC18F6390/6490/8390/8490 The pins of the EUSART are multiplexed with the functions of PORTC RC7/RX1/DT1). In order to configure these pins as an EUSART: • ...
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... Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39629C-page 198 R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...