PIC18LF2685-I/SO Microchip Technology, PIC18LF2685-I/SO Datasheet - Page 80

• Manufacturer Part Number: PIC18LF2685-I/SO
• Description: 96KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2685-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2682/2685/4682/4685
TABLE 5-2:
DS39761C-page 80
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
Mode 0
IPR3
Mode 1, 2
PIR3
Mode 0
PIR3
Mode 1, 2
PIE3
Mode 0
PIE3
Mode 1, 2
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1:
File Name
(3)
(3)
2:
3:
4:
5:
6:
7:
8:
9:
(3)
(3)
(3)
(3)
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
CAN bits have multiple functions depending on the selected mode of the CAN module.
This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
These registers and/or bits are available on PIC18F4682/4685 devices only.
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Address Register Low Byte
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
LATD Data Output Register
LATC Data Output Register
LATB Data Output Register
TRISA7
PSPIP
PSPIE
OSCFIP
OSCFIE
PSPIF
INTSRC
LATA7
OSCFIF
EEPGD
CSRC
SPEN
IRXIP
IRXIP
IRXIF
IRXIF
IRXIE
IRXIE
Bit 7
RD7
RC7
IBF
—
—
—
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
(3)
(3)
(3)
(6)
(6)
TRISA6
PLLEN
LATA6
CMIP
CMIE
CMIF
WAKIP
WAKIP
WAKIF
WAKIF
WAKIE
WAKIE
CFGS
ADIP
ADIF
ADIE
Bit 6
OBF
RX9
RD6
RC6
TX9
—
—
—
(9)
(9)
(9)
(6)
(4)
(6)
PORTA Data Direction Register
LATA Data Output Register
ERRIP
ERRIP
ERRIF
ERRIF
ERRIE
ERRIE
SREN
TXEN
RCIP
RCIE
IBOV
RCIF
Bit 5
RD5
RC5
—
—
—
—
—
—
—
—
PSPMODE
TXB2IP
TXBnIP
TXB2IE
TXBnIE
TXB2IF
TXBnIF
SYNC
CREN
FREE
TUN4
EEIP
EEIF
EEIE
TXIP
TXIE
Bit 4
TXIF
RD4
RC4
—
—
—
TXB1IP
TXB1IF
TXB1IE
WRERR
SENDB
ADDEN
TXB1IP
TXB1IF
TXB1IE
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
RE3
TUN3
Bit 3
RD3
RC3
—
—
—
(5)
(8)
(8)
(8)
LATE Data Output Register
TXB0IP
TXB0IF
TXB0IE
TXB0IE
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TXB0IP
TXB0IF
WREN
RE2
BRGH
FERR
TUN2
Bit 2
RD2
RC2
—
(3)
(8)
(8)
(8)
EEPROM Addr Register High Byte ---- --00 53, 110
TMR3IP
TMR3IE
TMR2IP
TMR2IE
RXB1IP
RXBnIP
RXB1IF
RXBnIF
RXB1IE
RXBnIE
TMR3IF
TMR2IF
TRISE1
OERR
RE1
TRMT
TUN1
Bit 1
RD1
RC1
WR
(3)
© 2009 Microchip Technology Inc.
ECCP1IP
ECCP1IE
ECCP1IF
FIFOWMIP
FIFOWMIF
FIFOMWIE
TMR1IP
TMR1IE
RXB0IP
RXB0IF
RXB0IE
TMR1IF
TRISE0
RE0
RX9D
TUN0
TX9D
Bit 0
RD0
RC0
RD
(3)
(9)
(9)
(9)
0000 0000 53, 233
0000 0000 53, 233
0000 0000 53, 240
0000 0000 53, 238
0000 0010 53, 239
0000 000x 53, 239
0000 0000 53, 107
0000 0000 53, 107
0000 0000 53, 107
xx-0 x000 53, 107
1111 1111 53, 128
1111 1111 53, 128
0000 0000 53, 122
0000 0000 53, 122
0000 0000 53, 125
0000 0000 53, 125
11-1 1111 53, 127
00-0 0000 54, 121
00-0 0000 54, 124
1111 1111 54, 126
0000 0000 54, 120
0000 0000 54, 123
0q-0 0000
0000 -111 54, 143
1111 1111 54, 140
1111 1111 54, 137
1111 1111 54, 134
1111 1111 54, 131
---- -xxx 54, 143
xxxx xxxx 54, 140
xxxx xxxx 54, 137
xxxx xxxx 54, 134
xxxx xxxx 54, 131
---- xxxx 54, 147
xxxx xxxx 54, 140
xxxx xxxx 54, 137
POR, BOR
Value on
on page:
Details
29, 54