PIC18LF2685-I/SO Microchip Technology, PIC18LF2685-I/SO Datasheet - Page 46

• Manufacturer Part Number: PIC18LF2685-I/SO
• Description: 96KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2685-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2682/2685/4682/4685
4.4
PIC18F2682/2685/4682/4685 devices implement a
BOR circuit that provides the user with a number of
configuration and power-saving options. The BOR
is controlled
BOREN1:BOREN0 Configuration bits. There are a total
of four BOR configurations which are summarized in
Table 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any value of BOREN1:BOREN0,
except ‘00’), any drop of V
D005) for greater than T
the device. A Reset may or may not occur if V
below V
Brown-out Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.
BOR
independently configured. Enabling Brown-out Reset
does not automatically enable the PWRT.
4.4.1
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
TABLE 4-1:
DS39761C-page 46
DD
BOREN1
BOR Configuration
rises above V
0
0
1
1
and
BOR
for
Brown-out Reset (BOR)
SOFTWARE ENABLED BOR
for less than T
the
an
BOREN0
by
BOR CONFIGURATIONS
DD
additional
BOR
Power-on
0
1
0
1
DD
rises above V
the
DD
; it then will keep the chip in
drops below V
BOR
BOR
DD
rises above V
(RCON<6>)
Unavailable
Unavailable
Unavailable
(parameter 35) will reset
SBOREN
below V
Available
BORV1:BORV0
Status of
. The chip will remain in
time
Timer
BOR
BOR
delay,
, the Power-up
BOR
(PWRT)
BOR
(parameter
BOR disabled; must be enabled by reprogramming the Configuration bits.
BOR enabled in software; operation controlled by SBOREN.
BOR enabled in hardware in Run and Idle modes, disabled during Sleep
mode.
BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
.
while the
DD
T
PWRT
falls
and
are
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by elimi-
nating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
4.4.2
When BOR is enabled, the BOR bit always resets to ‘0’
on any Brown-out Reset or Power-on Reset event. This
makes it difficult to determine if a Brown-out Reset
event has occurred just by reading the state of BOR
alone. A more reliable method is to simultaneously
check the state of both POR and BOR. This assumes
that the POR bit is reset to ‘1’ in software immediately
after any Power-on Reset event. IF BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a Brown-out
Reset event has occurred.
4.4.3
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
BOR Operation
Even when BOR is under software control,
the Brown-out Reset voltage level is still
set by the BORV1:BORV0 Configuration
bits. It cannot be changed in software.
DETECTING BOR
DISABLING BOR IN SLEEP MODE
© 2009 Microchip Technology Inc.