PIC18LF2685-I/SO Microchip Technology, PIC18LF2685-I/SO Datasheet - Page 243

• Manufacturer Part Number: PIC18LF2685-I/SO
• Description: 96KB Flash, 3KB RAM, ECAN, 1024 EEPROM 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2685-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.2.5
The Enhanced EUSART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter transmit consists of a Start bit, followed by twelve
‘0’ bits and a Stop bit. The frame Break character is
sent whenever the SENDB and TXEN bits (TXSTA<3>
and TXSTA<5>) are set while the Transmit Shift
register is loaded with data. Note that the value of data
written to TXREG will be ignored and all ‘0’s will be
transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 18-10 for the timing of the Break
character sequence.
18.2.5.1
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
FIGURE 18-10:
© 2009 Microchip Technology Inc.
Reg. Empty Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
TRMT bit
TX (pin)
TXIF bit
SENDB
BREAK CHARACTER SEQUENCE
Break and Sync Transmit Sequence
SEND BREAK CHARACTER SEQUENCE
Dummy Write
SENDB sampled here
Start Bit
PIC18F2682/2685/4682/4685
Bit 0
Bit 1
Break
1.
2.
3.
4.
5.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
18.2.6
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 18.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to set up the
Break character.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
RECEIVING A BREAK CHARACTER
Bit 11
Auto-Cleared
Stop Bit
DS39761C-page 243