PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 61

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks to the device continue while the INTOSC source
stabilizes after an interval of T
Table
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
FIGURE 4-3:
FIGURE 4-4:
 2009-2011 Microchip Technology Inc.
31-13).
LF-INTOSC
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Note 1: T
Counter
OSC1
Clock
Clock
CPU
Multiplexer
CPU Clock
PLL Clock
Peripheral
Program
INTOSC
Counter
2: Clock transition typically occurs within 2-4 T
Output
OSC1
Clock
Q1
OST
SCS<1:0> bits Changed
Q2
PC
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
= 1024 T
Q3
Q4
OSC
Q1
IOBST
; T
Q1
PLL
1
T
OST
(Parameter 39,
= 2 ms (approx). These intervals are not shown to scale.
(1)
PC
2
Q2
Clock Transition
OSC
3
T
OSTS bit Set
Q3
PLL
.
(1)
(1)
PC + 2
OSC
n-1
Q4
.
PIC18F87K22 FAMILY
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
(2)
Q2
PC + 2
Q3
Q2
Q4
Q3 Q4
Figure
Q1
Q1
4-4). When the clock
Q2
PC + 4
PC + 4
Q2
DS39960D-page 61
Q3
Q3