PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 326

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
TABLE 21-4:
DS39960D-page 326
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSP1MSK
SSP1CON1
SSP1CON2
SSP1STAT
SSP2BUF
SSP2ADD
SSP2MSK
SSP2CON1
SSP2CON2
SSP2STAT
PMD0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
2:
(1)
(1)
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
Slave operating modes in 7-Bit Masking mode. See
more details.
Alternate bit definitions for use in I
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP1 Baud Rate Reload Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
MSSP2 Baud Rate Reload Register (I
GIE/GIEH PEIE/GIEL
TMR5GIF
TMR5GIE
TMR5GIP
CCP3MD
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISD7
REGISTERS ASSOCIATED WITH I
WCOL
WCOL
PSPIF
PSPIE
PSPIP
GCEN
GCEN
GCEN
GCEN
MSK7
MSK7
Bit 7
SMP
SMP
ACKSTAT
ACKSTAT
ACKSTAT
ACKSTAT
CCP2MD
TRISC6
TRISD6
SSPOV
SSPOV
MSK6
MSK6
ADIE
ADIP
Bit 6
ADIF
CKE
CKE
—
—
—
—
—
—
ADMSK5
ADMSK5
CCP1MD
TMR0IE
SSP2IF
SSP2IE
SSP2IP
TRISC5
TRISD5
2
2
SSPEN
ACKDT
SSPEN
ACKDT
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
MSK5
MSK5
C Slave mode),
C Slave mode),
Bit 5
D/A
D/A
2
C Slave mode operations only.
(2)
(2)
2
2
C Master mode)
C Master mode)
ADMSK4
ADMSK4
UART2MD UART1MD
TRISC4
TRISD4
BLC2IE
BLC2IP
ACKEN
ACKEN
BLC2IF
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
MSK4
MSK4
Bit 4
CKP
CKP
2
C™ OPERATION
P
P
Section 21.4.3.4 “7-Bit Address Masking Mode”
(2)
(2)
ADMSK3
ADMSK3
CTMUIE
CTMUIP
CTMUIF
SSP1IE
SSP1IP
TRISC3
TRISD3
SSP1IF
BCL1IE
BCL1IP
BCL1IF
SSPM3
SSPM3
MSK3
RCEN
MSK3
RCEN
RBIE
Bit 3
S
S
(2)
(2)
ADMSK2
ADMSK2
TMR1GIF
TMR1GIE
TMR1GIP
SSP2MD
 2009-2011 Microchip Technology Inc.
TMR0IF
HLVDIE
HLVDIP
CCP2IF
CCP2IE
CCP2IP
TRISC2
TRISD2
HLVDIF
SSPM2
SSPM2
MSK2
MSK2
Bit 2
PEN
PEN
R/W
R/W
(2)
(2)
ADMSK1
ADMSK1
SSP1MD
TMR2IE
TMR2IP
TMR3IE
TMR3IP
2
TMR2IF
TMR3IF
CCP1IF
CCP1IE
CCP1IP
TRISC1
TRISD1
SSPM1
SSPM1
INT0IF
MSK1
RSEN
MSK1
RSEN
C™ mode.
Bit 1
UA
UA
(2)
(2)
TMR3GIE
TMR3GIP
TMR3GIF
TMR1IF
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
ADCMD
TRISC0
TRISD0
SSPM0
SSPM0
MSK0
MSK0
RBIF
Bit 0
SEN
SEN
SEN
SEN
2
BF
BF
C
for