PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 519

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 31-19:
TABLE 31-22: I
 2011 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
Note:
SCLx
SDAx
In
SDAx
Out
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If
such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
T
is released.
R
:
:
:
:
:
STA
DAT
STO
STA
DAT
max. + T
Refer to
2
Clock High Time
Clock Low Time
SDAx and SCLx Rise Time 100 kHz mode
SDAx and SCLx Fall Time 100 kHz mode
Start Condition Setup Time 100 kHz mode
Start Condition Hold Time
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time 100 kHz mode
Output Valid from Clock
Bus Free Time
Bus Capacitive Loading
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
SU
I
2
90
2
:
C™ BUS DATA TIMING
Figure 31-3
DAT
C™ bus device can be used in a Standard mode I
103
= 1000 + 250 = 1250 ns (according to the Standard mode I
91
Characteristic
109
for load conditions.
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
MSSP module
400 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
PIC18F87K22 FAMILY
20 + 0.1 C
20 + 0.1 C
107
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
2
C bus system, but the requirement, T
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification), before the SCLx line
Units
pF
 s
 s
 s
 s
ns
ns
ns
ns
 s
 s
 s
 s
ns
 s
ns
ns
 s
 s
ns
ns
 s
 s
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free before
a new transmission can start
92
B
B
102
is specified to be from
is specified to be from
110
Conditions
DS39960D-page 519
SU
:
DAT
 250 ns,