PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 36

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PIC18F85K22-I/PT

Manufacturer Part Number
PIC18F85K22-I/PT
Description
IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F85K22-I/PT

Controller Family/series
PIC18
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Core Size
8 Bit
Program Memory Size
32KB
Core Processor
PIC
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC18F87K22 FAMILY
TABLE 1-4:
DS39960D-page 36
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
V
V
AV
AV
ENVREG
V
Legend: TTL = TTL compatible input
Note 1:
SS
DD
DDCORE
SS
DD
RJ0
ALE
RJ1
OE
RJ2
WRL
RJ3
WRH
RJ4
BA0
RJ5
CE
RJ6
LB
RJ7
UB
V
V
DDCORE
CAP
2:
3:
4:
5:
Pin Name
/V
ST = Schmitt Trigger input with CMOS levels
I
P
I
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
Not available on PIC18F65K22 and PIC18F85K22 devices.
PSP is available only in Microcontroller mode.
The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
CAP
2
C = I
= Input
= Power
PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
2
C™/SMBus
11, 31, 51, 70
Pin Number
32, 48, 71
TQFP
62
61
60
59
39
40
41
42
26
25
24
12
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
P
P
P
P
P
I
Buffer
Type
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTJ is a bidirectional I/O port.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
Core logic power or external filter capacitor connection.
Digital I/O.
External memory address latch enable.
Digital I/O.
External memory output enable.
Digital I/O.
External memory write low control.
Digital I/O.
External memory high control.
Digital I/O.
External Memory Byte Address 0 control
Digital I/O
External memory chip enable control.
Digital I/O.
External memory low byte control.
Digital I/O.
External memory high byte control.
External filter capacitor connection (regulator
enabled/disabled).
CMOS = CMOS compatible input or output
Analog = Analog input
O
OD
= Output
= Open-Drain (no P diode to V
Description
 2009-2011 Microchip Technology Inc.
DD
)

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