CLC021AVGZ-3.3 National Semiconductor, CLC021AVGZ-3.3 Datasheet - Page 5

• Manufacturer Part Number: CLC021AVGZ-3.3
• Description: IC, DIG VIDEO SERIALIZER, 3.63V, PQFP-44
• Manufacturer: National Semiconductor

Specifications of CLC021AVGZ-3.3

• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 2.97V To 3.63V
• Power Dissipation Pd: 235mW
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PQFP
• No. Of Pins: 44
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

V
V
V
I
BR
F
t
t
t
t
t
t
t
L
R
BR
F
t
t
t
t
t
t
t
DD
r
j
jit
r
LOCK
SU
HLD
r
j
jit
r
LOCK
SU
HLD
Symbol
Symbol
Symbol
, t
, t
GEN
, t
, t
OH
OL
SDO
P CLK
P CLK
DC Electrical Characteristics—CLC021AVGZ-3.3
GEN
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
AC Electrical Characteristics—CLC021AVGZ-5.0
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
AC Electrical Characteristics—CLC021AVGZ-3.3
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
SDO
SDO
f
f
f
f
CMOS Output Voltage
High Level
CMOS Output Voltage
Low Level
Serial Driver Output
Voltage
Power Supply Current,
Total
Serial Data Rate
Reference Clock
Input Frequency
Reference Clock Duty
Cycle
Rise Time, Fall Time
Serial Output Jitter
Serial Output Jitter
Rise Time, Fall Time
Output Overshoot
Lock Time
Setup Time
Hold Time
Output Inductance
Output Resistance
Serial Data Rate
Reference Clock
Input Frequency
Reference Clock Duty
Cycle
Rise Time, Fall Time
Serial Output Jitter
Serial Output Jitter
Rise Time, Fall Time
Output Overshoot
Lock Time
Setup Time
Hold Time
Parameter
Parameter
Parameter
(Note 5)
270 Mbps,Figure 2, (Note 6)
(Notes 4, 5)
20%–80%, (Notes 4, 5)
(Note 4)
(Notes 5, 7)
Figure 3 (Note 4)
Figure 3 (Note 4)
(Note 4)
(Note 4)
(Note 5)
270 Mbps,Figure 2, (Note 6)
(Notes 4, 5)
20%–80%, (Notes 4, 5)
(Note 4)
(Notes 5, 7)
Figure 3 (Note 4)
Figure 3 (Note 4)
I
I
R
R
Figure 2
R
R
P
Colour Bar Pattern,
Figure 2
OH
OL
CLK
L
REF
L
REF
= 75Ω 1%,
= 75Ω 1%,
= +8 mA
= −8 mA
= 27 MHz, NTSC
= 1.69 kΩ 1%,
= 1.69 kΩ 1%,
Conditions
Conditions
Conditions
5
All CMOS
Outputs
SDO, SDO
Reference
SDO, SDO
P
P
D
SDO, SDO
D
D
SDO, SDO
SDO, SDO
P
P
D
SDO, SDO
D
D
CLK
CLK
N
N
N
CLK
CLK
N
N
N
, P
, P
Reference
Reference
to P
from P
to P
from P
CLK
CLK
CLK
CLK
(Continued)
CLK
CLK
Min
720
2.4
0.0
Min
100
500
Min
100
500
1.0
1.0
10
45
10
45
3
3
4
4
Typ
800
3.0
0.3
33
Typ
220
100
800
Typ
220
100
800
25k
1.5
1.5
50
75
50
75
1
2
2
6
1
2
2
V
SS
Max
V
880
55
+ 0.5V
DD
1500
1500
Max
Max
400
200
400
200
3.0
3.0
40
55
40
55
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mV
Units
Mbps
Units
Mbps
Units
ps
ps
ps
ps
MHz
MHz
mA
nH
ns
ps
µs
ns
ns
ns
ps
µs
ns
ns
%
%
%
%
Ω
V
V
P-P
P-P
P-P
P-P
P-P