CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 89

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
CLRC632_35
Product data sheet
PUBLIC
11.3.2.1 Using the Receive command
11.3.2.2 RF channel redundancy and framing
11.3.2.3 Collision detection
Remark: This command may be used for test purposes only, since there is no timing
relation to the Transmit command.
After starting the Receive command the internal state machine decrements the RxWait
register value on every bit-clock. The analog receiver circuitry is prepared and activated
from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the
incoming signal using the RF interface. If the signal strength reaches a level above the
value set in the RxThreshold register’s MinLevel[3:0] bits, the receiver starts decoding.
The decoder stops when the signal cannot be detected on the receiver input pin RX. The
decoder sets the RxIRq flag bit to indicate that the operation has finished.
The receive sequence phases can be monitored using bits ModemStatus[2:0] in the
PrimaryStatus register; see
Remark: The minimum value for RxWait[7:0] is 3 because counter values from 3 to 0 are
needed to initialize the analog receiver circuitry.
In ISO/IEC 15693 mode, the decoder expects a SOF pattern at the beginning of each data
stream. When a SOF is detected, it activates the serial-to-parallel converter and gathers
the incoming data bits. If an EOF pattern (ISO/IEC 15693) is detected or the signal
strength falls below the MinLevel value, the receiver and the decoder stop, the Idle
command is entered and an appropriate response for the microprocessor is generated
(interrupt request activated, status flags set).
In I-CODE1 mode, the decoder does not expect a SOF pattern at the beginning of each
data stream. It activates the serial-to-parallel converter on the first received bit of the data.
Every full byte is then sent to the FIFO buffer.
If ChannelRedundancy register bit RxCRCEn is set a CRC block is expected. The CRC
block may be one byte or two bytes based on the ChannelRedundancy register’s CRC8
bit.
Remark: If it is correct, the CRC block is not forwarded to the FIFO buffer. The CRC is
realized by shifting the incoming data bytes through an internal buffer of one or two bytes
(depending on the defined CRC). The CRC block remains in this internal buffer.
Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the
CRC fails, all bytes received are forwarded to the FIFO buffer (including the faulty CRC).
If more than one label is within the RF field during the label selection phase, they will
respond simultaneously. The CLRC632 supports the algorithm defined in ISO/IEC 15693
as well as the I-CODE1 anti-collision algorithm to resolve label serial number data
collisions using the anti-collision procedure. The basis for this procedure is the ability to
detect bit-collisions.
Bit-collision detection is supported by the Manchester coding bit encoding scheme used.
If in the first and second half-bit of a bit a subcarrier modulation is detected, instead of
forwarding a 1-bit or a 0-bit, a bit-collision is flagged.
Rev. 3.5 — 10 November 2009
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
Section 11.2.4 on page
073935
85.
CLRC632
© NXP B.V. 2009. All rights reserved.
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