CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 17

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
Table 17.
CLRC632_35
Product data sheet
PUBLIC
EEPROM
byte
address
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
Content of I-CODE1 startup configuration
Register
address
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Value
00h
58h
3Fh
05h
2Ch
3Fh
3Fh
00h
00h
8Bh
00h
54h
68h
00h
41h
00h
00h
08h
0Ch
FEh
FFh
00h
00h
00h
00h
3Eh
0Bh
02h
00h
02h
00h
00h
Symbol
Page
TxControl
CwConductance
ModGsCfgh
CoderControl
ModWidth
ModWidthSOF
TypeBFraming
Page
RxControl1
DecoderControl
BitPhase
RxThreshold:
BPSKDemControl
RxControl2
ClockQControl
Page
RxWait
ChannelRedundancy
CRCPresetLSB
CRCPresetMSB
TimeSlot Period
MFOUTSelect
PreSet27
Page
FIFOLevel
TimerClock
TimerControl
TimerReload
IRQPinConfig
PreSet2E
PreSet2F
Rev. 3.5 — 10 November 2009
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
Description
free for user
transmitter pins TX1 and TX2 switched off, bridge driver
configuration, modulator driven from internal digital circuitry
source resistance (R
source resistance (R
modulation, to determine the modulation index
selects the bit coding mode and the framing during
transmission
pulse width for code used (1 out of 256, NRZ or 1 out of 4)
pulse coding is set to standard configuration
pulse width of SOF
-
free for user
amplifier gain is maximum
bit-collisions always evaluate to HIGH in the data bit stream
BitPhase[7:0] is set to standard configuration
MinLevel[3:0] and CollLevel[3:0] are set to maximum
-
use Q-clock for the receiver, automatic receiver off is
switched on, decoder is driven from internal analog circuitry
automatic Q-clock calibration is switched on
free for user
frame guard time is set to eight bit-clocks
channel redundancy is set using I-CODE1
CRC preset value is set using I-CODE1
CRC preset value is set using I-CODE1
defines the time for the I-CODE1 time slots
pin MFOUT is set LOW
-
free for user
WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
TPreScaler[4:0] is set to standard configuration, timer unit
restart function is switched off
Timer is started at the end of transmission, stopped at the
beginning of reception
the timer unit preset value is set to standard configuration
pin IRQ is set to high-impedance
-
-
S
S
) of TX1 and TX2 to minimum
) of TX1 and TX2 at the time of
CLRC632
© NXP B.V. 2009. All rights reserved.
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