CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 80

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
CLRC632_35
Product data sheet
PUBLIC
11.2.1.2 RF channel redundancy and framing
11.2.1.3 Transmission of bit oriented frames
11.2.1.4 Transmission of frames with more than 64 bytes
Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern,
followed by the data stream and is closed by an End Of Frame (EOF) pattern. These
different phases of the transmission sequence can be monitored using the PrimaryStatus
register ModemState[2:0] bit; see
Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is
calculated and appended to the data stream. The CRC is calculated according to the
settings in the ChannelRedundancy register. Parity generation is handled according to the
ChannelRedundancy register ParityEn and ParityOdd bits settings.
The transmitter can be configured to send an incomplete last byte. To achieve this the
BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This
is shown in
Figure 16
All fully transmitted bytes are followed by a parity check bit but the incomplete byte is not
followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are automatically
cleared.
Remark: If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be
disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit.
To generate frames of more than 64 bytes, the microprocessor must write data to the
FIFO buffer while the Transmit command is active. The state machine checks the FIFO
buffer status when it starts transmitting the last bit of the data stream; the check time is
marked in
Fig 16. Transmitting bit oriented frames
TxLastBits = 0
TxLastBits = 7
TxLastBits = 1
shows the data stream if bit ParityEn is set in the ChannelRedundancy register.
Figure 17
Figure
16.
SOF
SOF
SOF
with arrows.
Rev. 3.5 — 10 November 2009
0
0
0
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
Section 11.2.4 on page
7
7
7
P
P
P
0
0
0
EOF
85.
6
CLRC632
© NXP B.V. 2009. All rights reserved.
7
EOF
P
EOF
001aak618
80 of 126