HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 7

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(INVERTED AT THE I/O PAD)
or GWA F804 - 11)
(GWA F807 - 15:0)
Input Select/Format Block
Each front end block and the level detector block contains an
input select/format block. A functional block diagram is
provided in the above figure. The input source can be any of
the four parallel input busses (See Microprocessor Interface
section, Table 3, “CHANNEL INPUT SELECT/FORMAT
REGISTER (IWA = *000h),” on page 32 or a test register
loaded via the processor bus (see Microprocessor Interface
section, Table 42, “mP/TEST INPUT BUS REGISTER (GWA
= F807h),” on page 45).
The input to the part can operate in a gated or interpolated
mode. Each input channel has an input enable (ENIx, x = A,
B, C or D). In the gated mode, one input sample is
processed per clock that the ENIx signal is asserted (low).
Processing is disabled when ENIx is high. The ENIx signal is
pipelined through the part to minimize delay (latency). In the
interpolated mode, the input is zeroed when the ENIx signal
is high, but processing inside the part continues. This mode
TESTENSTRB
(IWA *000 - 11
GWA F804 - 14:13)
EXTERNAL DATA
(IWA *000 - 14:13
(GWA F808)
TESTENBIT
NOTE: ENI* SIGNALS
REGISTER
INPUT SELECT
ARE ACTIVE HIGH
μP TEST
A(15:0)
B(15:0)
C(15:0)
D(15:0)
ENIA
ENIB
ENIC
ENID
or
or GWA F804 - 12)
(IWA *000 - 12
TEST ENI
SELECT
FREQUENCY (COF)
CARRIER OFFSET
7
TESTEN
15:0
15:0
ENI
COF SYNC
or GWA F804 - 15)
EXTERNAL/TEST
(IWA *000 - 15
SELECT
(1WA *000 - 2)
INPUT ENABLE HOLD OFF
ENABLE
COF
(ENABLED BY SYNCI)
15:0
EN
TWO’s COMPLEMENT
(GWA F802 - 30)
or GWA F804 - 10)
OFFSET BINARY
(IWA *000 - 10
FORMAT
(IWA *000 - 0)
OR
ENABLE PN
HSP50216
COF TO
CARRIER
NCO/MIXER
COF SYNC TO
CARRIER
NCO/MIXER
PN
or GWA F804 - 8:7)
FLOATING POINT
inserts zeros between the data samples, interpolating the
input data stream up to the clock rate. On reset, the part is
set to gated mode and the input enables are disabled. The
inputs are enabled by the first SYNCI signal.
The input section can select one channel from a multiplexed
data stream of up to 8 channels. The input enable is delayed
by 0 to 7 clock cycles to enable a selection register. The
register following the selection register is enabled by the
non-delayed input enable to realign the processing of the
channels. The one-clock-wide input enable must align with
the data for the first channel. The desired channel is then
selected by programming the delay. A delay of zero selects
the first channel, a delay of 1 selects the second, etc.
(IWA *000 - 8:7
FIXED POINT
11/3, 12/3,
13/3, 14/2
or GWA F8O4 - 6:4)
PROGRAMMABLE
DE-MULTIPLEX
CONTROL (0-7)
TO
(IWA *000 - 6:4
OFFSET FREQUENCY
DELAY
PN TO
CARRIER
NCO/MIXER
RESAMPLER
SOF SYNC
FLOATING POINT
or GWA F804 - 9)
FIXED POINT
(IWA *000 - 9
(SOF)
OR
(IWA *000 - 1)
INTERPOLATED/GATED
ENABLE
SOF
or GWA F804 - 3)
R
E
G
(IWA *000 - 3
MODE
15:0
SOF TO
RESAMPLER
NCO
SOF SYNC TO
RESAMPLER
NCO
August 17, 2007
DATA
TO
NCO/MIXER
OR
LEVEL
DETECTOR
DATA
SAMPLE
ENABLE
FN4557.6