HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 22

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resampler
The resampler is an NCO controlled polyphase filter that allows
the output sample rate to have a non-integer relationship to the
input sample rate. The filter engine can be viewed conceptually
as a fixed interpolate-by-32 filter, followed by an NCO controlled
decimator. The Resampler NCO is similar to the carrier NCO
phase accumulator but does not include the SIN/COS section.
It provides the resampler output pulse and associated phase
information to logic that determines the nearest of the 32
available phase points for a given output sample.
The center frequency (output sample rate) control is double
buffered, i.e., the control word is written to one register via the
microprocessor interface and then transferred to another
(active) register on a write to the timing NCO center frequency
update strobe location (IWA register *009h) or on a SYNCI (if
enabled). As it is not possible to represent some frequencies
exactly with an NCO and therefore, phase error accumulates
eventually causing a bit slip, the phase accumulator length
has been sized to where the error is insignificant. At a
resampler input rate of 1MHz, half an LSB of error in loading
the 56-bit accumulator is 7*10
accumulated phase error is only 0.2*10
degree). The NCO update by the filter compute engine is
typically at the resampler's input rate, and is enabled by the
IncrRS bit in the filter instruction word. The NCO then rolls
over at a fraction of the resampler input rate. The output
sample rate is (f
rate and N is the phase accumulated per resampler input
sample. N must be between 40000000000000h and
FFFFFFFFFFFFFFh corresponding to decimations from 4 to
(1 + 2
80000000000000h to FFFFFFFFFFFFFFh (providing
decimation from 2 to (1 + 2
most applications since integer decimation can be done more
efficiently in the preceding CIC and halfband filters. The
resampler changes the sample rate by computing an output at
each input which causes the NCO to roll over. If an output is to
be computed, the nearest of the 32 available points from the
polyphase structure is used. Because outputs are generated
only on input samples which cause an NCO roll over, output
samples will in general not be evenly spaced. The
FIFO/TIMER block between the filter compute engine and the
AGC is provided to improve output sample spacing for
presentation to the serial data output formatter section (see
IWA=*00Ah bits 11:0 description). If D/A converted directly,
there would be artifacts from the uneven sample spacing, but
if the samples are stored and reconstructed at the proper rate
(the NCO rollover rate), the signal would have only the
distortion produced by interpolation image leakage and the
time quantization (phase jitter) due to the finite number of
interpolation filter phases.
The polyphase filter has 192 coefficients implemented as 32
phases, each of which having 6 taps (6 x 32 = 192). These
coefficients are provided in Table 50. The stopband
-56
), respectively. Generally, however, a range of
IN
/ 2
56
)*N, where f
-56
22
-12
), respectively) is sufficient for
degrees. After 1 year, the
IN
is the resampler input
-3
of a bit (< 1/10 of a
HSP50216
attenuation of the filter is greater than 60dB, as shown in
Figures 13 through 15. The signal to total image power ratio
is approximately 55dB, due to the aliasing of the
interpolation images. If the output is at least 2x the baud
rate, the 32 interpolation phases yield an effective sample
rate of 64x the baud rate or approximately 1.5% (1/64
resampler input sample period) maximum timing error.
AGC
The AGC Section provides gain to small signals, after the
large signals and out-of-band noise have been filtered out, to
ensure that small signals have sufficient bit resolution in the
output formatter. The AGC can also be used to manually set
the gain. The AGC optimizes the bit resolution for a variety
of input amplitude signal levels. The AGC loop automatically
adds gain to bring small signals from the lower bits of the
24-bit programmable FIR filter output into the range of 20-bit
and shorter words in the output section. Without gain control,
a signal at -72dBFS = 20log
have only 4 bits of resolution at the output if a 16 bit word
length were to be used (12 bits less than the full scale 16
bits). The potential increase in the bit resolution due to
processing gain of the filters can be lost without the use of
the AGC.
Figure 1 shows the Block Diagram for the AGC Section. The
FIR filter data output is routed to the Cartesian to polar
coordinate converter after passing through the AGC
multipliers and shift registers. The magnitude output of the
Cartesian to polar coordinate converter is routed through the
AGC error detector, the AGC error scaler and into the AGC
loop filter. This filtered error term is used to drive the AGC
multiplier and shifters, completing the AGC control loop.
The AGC multiplier/shifter portion of the AGC is identified in
Figure 1. The gain control from the AGC loop filter is
sampled when new data enters the multiplier/shifter. The
limit detector detects overflow in the shifter or the multiplier
and saturates the output of I and Q data paths
independently. The shifter has a gain from 0 to 90.31dB in
6.021dB steps, where 90.31dB = 20log
N = 15. The mantissa provides up to an additional 6.02dB of
gain. The gain in dB from the mantissa is:
20log
mantissa interpreted as an unsigned integer ranging from 0
to 2
Thus, the AGC multiplier/shifter transfer function is
expressed as:
AGC Mult/Shift Gain = 2
where N, the shifter exponent, has a range of 0 < N < 15 and
X, the mantissa, has a range of 0 < X < (2
14
10
- 1.
[1 + (X)2
-14
], where X is the fractional part of the
N
[1 + (X)2
10
(2
-12
-14
) at the input would
]
10
(2
14
N
-1).
) when
August 17, 2007
FN4557.6