HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 24

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The loop gain register values adjust the response/settling
time of the AGC loop. The loop gain is set in the AGC Error
Scaling circuitry, using four values in two sets of
programmable mantissa and exponent pairs (see IWA
register *010h). Each set has both an attack and a decay
gain. This allows asymmetric adjustment for applications
such as VOX systems where the signal turns on and off. In
these applications, the gains would be set for fast attack and
slow decay so that the part decreases the gain quickly when
the signal turns on, but increases the gain slowly when the
signal turns off (in anticipation of it turning back on shortly).
For fixed gains, either set the upper and lower AGC limits to
the same value, or set the limits to minimum and maximum
gains and set the AGC attack and decay loop gains to zero.
The mantissa, M, is a 4-bit value which weights the loop filter
input from 0.0 to 15/2
shift factor that provides additional weighting from 2
2
gain as given by,
AGC Loop Gain = M
where M
to 15, and E
0 to 15. The composite (shifter and multiplier) AGC scaling
Gain range is from 0.0000 to 2.329(0.9375)2
2.18344. The scaled gain error can range (depending on
threshold) from 0 to 2.18344, which maps to a “gain change
per sample” range of 0 to 3.275dB/sample.
The AGC attack and decay gain mantissa and exponent values
for loop gains 0 and 1 are programmed into IWA register *010h.
The PDC provides for the storing of two values of AGC attack
and decay scaling gains to allow for quick adjustment of the
loop gain by simply setting IWA register *013h bits 9 and 10
accordingly. Possible applications include acquisition/tracking,
no burst present/burst present, strong signal/weak signal,
track/hold, or fast/slow AGC values.
The AGC loop filter consists of an accumulator with a built in
limiting function. The maximum and minimum AGC gain
limits are provided to keep the gain within a specified range
and are programmed by 16-bit upper and lower limits using
the following the equation:
AGC Gain Limit = (1 + m
(AGC Gain Limit)dB = (6.02)(eeee) + 20 log(1.0+0.mmmm
mmmm mmmm)
where m is a 12-bit mantissa value between 0 and 4095, and
e is the 4-bit exponent ranging from 0 to 15. IWA register
*011h Bits 31:16 are used for programming the upper limit,
while bits 15:0 are used to program the lower limit. The
format for these limit values are:
(31:16) or (15:0): E E E E M M M M M M M M M M M M
for a gain of 0 1. M M M M M M M M M M M M * 2
-15
. Together the mantissa and exponent define the loop
LG
LG
is a 4-bit binary mantissa value ranging from 0
is a 4-bit binary exponent value ranging from
LG
4
= 0.9375. The exponent, E, defines a
2
AGC
-4
2
-(15-E
24
2
-12
) 2
LG
e
)
0
= 0.0000 to
E E E E
0
to
HSP50216
and the possible range of AGC limits from the previous
equations is 0 to 96.328dB. The bit weightings for the AGC
Loop Feedback elements are detailed in Table 51.
Using AGC loop gain, the AGC range, and expected error
detector output, the gain adjustments per output sample for
the loop filter section of the digital AGC can be given by
AGC Slew Rate = (1.5 dB) (THRESHOLD - (MAG *
1.64676)) x (M
The loop gain determines the growth rate of the sum in the
loop accumulator which, in turn, determines how quickly the
AGC gain scales the output to the threshold value. Since the
log of the gain response is roughly linear, the loop response
can be approximated by multiplying the maximum AGC gain
error by the loop gain. The expected range for the AGC rate
is ~ 0.000106 to 3.275dB/output sample time for a threshold
of 1/2 scale. For a full scale error, the minimum non-zero
AGC slew rate would be approximately 0.0002dB/output or
20dB/sec at 100ksps. The maximum gain would be
6dB/output. This much gain, however, would probably result
in significant AM on the output.
The maximum AGC Response is given by:
AGC Response
Gain)(AGC Loop Gain)(AGC Output Weighting)
Since the AGC error is scaled to adjust the gain, the loop
settles asymptotically to its final value. The loop settles to
the mean of the signal. For example, if M
E
gain mantissas and exponents are set in IWA register *010h,
with IWA register *013h selecting loop gain 0 or 1 and the
settling mode.
In the HSP50216, a SYNCI signal will clear the AGC loop
filter accumulator if GWA register F802h bit 27 is set.
The settling mode of the AGC forces either the mean or the
median of the signal magnitude error to zero, as selected by
IWA register *013h bit 8. For mean mode, the gain error is
scaled and used to adjust the gain up or down. This
proportional scaling mode causes the AGC to settle to the
final gain value asymptotically. This AGC settling mode is
preferred in many applications because the loop gain
adjustments get smaller and smaller as the loop settles,
reducing any AM distortion caused by the AGC.
With this AGC settling mode, the proportional gain error
causes the loop to settle more slowly if the threshold is
small. This is because the maximum value of the threshold
minus the magnitude is smaller. Also, the settling can be
asymmetric, where the loop may settle faster for “over
range” signals than for “under range” signals (or vice versa).
In some applications, such as burst signals or TDMA signals,
a very fast settling time and/or a more predictable settling
time is desired. The AGC may be turned off or slowed down
after an initial AGC settling period.
LG
= 1100, the AGC Loop Gain = 0.3125 * 2
LG
Max
) (2
= (Input)(Cart/Polar Gain)(Error Det.
-4
) (2
-(15 - E
LG
)
)
LG
= 0101 and
-7
. The loop
August 17, 2007
FN4557.6