HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 6

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
The HSP50216 is a four channel digital receiver integrated
circuit offering exceptional dynamic range and flexibility.
Each of the four channels consists of a front-end NCO,
digital mixer, and CIC-filter block and a back-end FIR, AGC
and Cartesian to polar coordinate-conversion block. The
parameters for the four channels are independently
programmable. Four parallel data input busses (A(15:0),
B(15:0), C(15:0) and D(15:0)) and four pairs of serial data
outputs (SDxA, SDxB, SDxC, and SDxD; x = 1 or 2) are
provided. Each input can be connected to any or all of the
internal signal processing channels, Channels 0, 1, 2 and 3.
The output of each channel can be routed to any of the serial
outputs. Outputs from more than one channel can be
multiplexed through a common output if the channels are
synchronized. The four channels share a common input
clock and a common serial output clock, but the output
sample rates can be synchronous or asynchronous. Bus
multiplexers between the front end and back end sections
provide flexible routing between channels for cascading
back-end filters or for routing one front end to multiple back
ends for polyphase filtering or systolic arrays (to provide
wider bandwidth filtering). A level detector is provided to
monitor the signal level on any of the parallel data input
busses, facilitating microprocessor control of gain blocks
prior to an A/D converter.
Each front end NCO/digital mixer/CIC filter section includes
a quadrature numerically controlled oscillator (NCO), digital
mixer, barrel shifter and a cascaded-integrator-comb filter
(CIC). The NCO has a 32-bit frequency control word for
16.3mHz tuning resolution at an input sample rate of
70MSPS. The SFDR of the NCO is >115dB. The barrel
shifter provides a gain of between 2
overflow in the CIC. The CIC filter order is programmable
between 1 and 5 and the CIC decimation factor can be
programmed from 4 to 512 for 5
32768 for 3
rd
order, or 65536 for 1
6
th
order, 2048 for 4
st
-45
or 2
and 2
nd
order filters.
-14
to prevent
th
order,
HSP50216
Each channel back end section includes an FIR processing
block, an AGC and a cartesian-to-polar coordinate
converter. The FIR processing block is a flexible filter
compute engine that can compute a single FIR or a set of
cascaded decimating filters. A single filter in a chain can
have up to 256 taps and the total number of taps in a set of
filters can be up to 384 provided that the decimation is
sufficient. The HSP50216 calculates 2 taps per clock (on
each channel) for symmetric filters, generally making
decimation the limiting factor for the number of taps
available. The filter compute engine supports a variety of
filter types including decimation, interpolation and
resampling filters. The coefficients for the programmable
digital filters are 22 bits wide. Coefficients are provided in
ROM for several halfband filter responses and for a
resampler. The AGC section can provide up to 96dB of
either fixed or automatic gain control. For automatic gain
control, two settling modes and two sets of loop gains are
provided. Separate attack and decay slew rates are provided
for each loop gain. Programmable limits allow the user to
select a gain range less than 96dB. The outputs of the
cartesian-to-polar coordinate conversion block, used by the
AGC loop, are also provided as outputs to the user for AM
and FM demodulation.
The HSP50216 supports both fixed and floating point
parallel data input modes. The floating point modes support
gain ranging A/D converters. Gated, interpolated and
multiplexed data input modes are supported. The serial data
output word width for each data type can be programmed to
one of ten output bit widths from 4-bit fixed point through
32-bit IEEE 754 floating point.
The HSP50216 is programmed through a 16-bit
microprocessor interface. The output data can also be read
via the microprocessor interface for all channels that are
synchronized. The HSP50216 is specified to operate to a
maximum clock rate of 70MSPS over the industrial
temperature range (-40°C to 85°C). The power supply
voltage range is 3.3V ± 0.15V. The I/Os are not 5V tolerant.
August 17, 2007
FN4557.6