HSP50216KIZ Intersil, HSP50216KIZ Datasheet
HSP50216KIZ
Specifications of HSP50216KIZ
Related parts for HSP50216KIZ
HSP50216KIZ Summary of contents
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... HSP50216KI HSP50216KI -40 to +85 196 Ld BGA HSP50216KIZ HSP50216KIZ -40 to +85 196 Ld BGA (Note) NOTE: These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Block Diagram μP TEST REGISTER INPUT SELECT, FORMAT, DEMUX A(15:0) INPUT SELECT, FORMAT, ENIA DEMUX B(15:0) ENIB INPUT SELECT, FORMAT, DEMUX C(15:0) ENIC INPUT SELECT, FORMAT, DEMUX D(15:0) ENID INPUT SELECT, FORMAT, DEMUX CLK RESET SYNCI SYNCO P(15:0) 2 HSP50216 ...
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Pinout B15 A0 B14 E B13 GND B12 F B11 VCC B10 G B9 GND GND H CLK VCC GND B6 ...
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Pin Descriptions NAME TYPE POWER SUPPLY Positive Power Supply Voltage, 3.3V ±0.15 VCC - GND - Ground, 0V. INPUTS A(15:0) I Parallel Data Input bus A. Sampled on the rising edge of clock when ENIA is active (low). B(15:0) I ...
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Pin Descriptions (Continued) NAME TYPE OUTPUTS SD1A O Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2, magnitude, phase, frequency (dφ/dt), AGC gain, and/or zeros. In addition, data outputs ...
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Functional Description The HSP50216 is a four channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, and CIC-filter block and a back-end FIR, AGC and Cartesian ...
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Input Select/Format Block TEST ENI SELECT (IWA *000 - 12 or GWA F804 - 12) μP TEST REGISTER 15:0 (GWA F807 - 15:0) TESTENBIT TESTEN (IWA *000 - 11 or GWA F804 - 11) TESTENSTRB (GWA F808) A(15:0) ENIA B(15:0) ...
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The parallel input busses are 16 bits wide. The input format may be twos complement or offset binary format. A floating point mode is also supported. The floating point modes and the mapping of the parallel 16-bit input format is ...
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MODE: 14-BIT MANTISSA, 2-BIT EXPONENT, 12dB EXPONENT RANGE EXPONENT GAIN (dB X15 01 6 X15 10 (Note 5) 12 X15 NOTE 11, the exponent input saturates at 10. Level Detector An input level detector is ...
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CIC Filter Next, the signal is filtered by a cascaded integrator/comb (CIC) filter. A CIC filter is an efficient architecture for decimation filtering. The power or magnitude squared frequency response of the CIC filter is given by: ⎛ ⎞ 2N ...
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Backend Data Routing FROM CIC DESTINATION BIT MAP (BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD AGC LOOP GAIN SELECT (PATH 01 ONLY) 27 UPDATE AGC ...
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Filter Compute Engine R/dφ/dt RAM 384 WORDS 0..-23 I INMUX (1:0) Q RAMR/Wb ADDRA (8:0) ADDRB (8:0) COEF (21:0), SHIFT (1:0) The filter compute engine is a dual multiply-accumulator (MAC) data path with a ...
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IWA = *00Ah bits 11:0. The number and order of the filtering in the filter chain is defined by a FIR control program. The FIR control ...
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Sample filter #2 requires: • 128 + 8 = 200 data RAM locations • (95+1)/2=48 coefficient RAM location (resampler and HBF coefficients are in ROM). The number of clock cycles required to compute an output for ...
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Filter Example #4 will be used to demonstrate this capability. Symbol rate of 4.096 MSym. The desired output sample rate is 8.192MSPS. Arrange the four back end sections as four filters operating on the same CIC output at a rate ...
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Filter Sequencer NEW DATA, FIR # INSTRUCTION RAM, RESET SEQUENCER SYNC THRESHOLD DECREMENT 1 WAIT COUNTER DECREMENT 2 LOOP LOOP COUNTER COUNTER PRELOAD RESAMPLER NCO 16 HSP50216 FIR# - WRITE DESTINATION FIR# - COMPUTE ALIAS POINTER MASK DATA ADDRESS STEP ...
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Instruction Bit Fields BIT POSITIONS FUNCTION 8:0 Instruction Instruction Field Bit Mapping Bit Type WAIT FIR JUMP (NOPs and loading the loop counter are special cases of the FIR instruction). 14:9 FIR Type FIR Parameter Bit Fields 14:9 000000 000001 ...
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BIT POSITIONS FUNCTION 28:18 Destination Destination Field Bit Mapping 28 AGCLFGN AGCLF AGCLFGNAGC loop gain select. Only applies to Path 1. AGCLF Path(1:0) Back End Data Routing Path Selection F(4:0) 31:29 Round Select 31:29 000 001 010 011 ...
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BIT POSITIONS FUNCTION 62:53 Coefficient Memory Memory base address of coefficients, 0-1023, 0-511 are valid on the HSP50216. Block Start 63 Reserved Set to 0. 66:64 Coefficient Memory 66:64 Memory Block Size Block Size ...
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BIT POSITIONS FUNCTION 122:120 Coefficient Memory (ADDRC) Usually set to 1. Step Size 122:120 125:123 Coefficient Memory (ADDRC) Usually set to 0. Block-to-Block Step 125:123 ...
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Single FIR Basic Program This is the basic program for a single FIR. This program applies to decimation filters (including DECx1) that are symmetric or asymmetric (but not complex). The FIR output is routed through path A with the AGC ...
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Resampler The resampler is an NCO controlled polyphase filter that allows the output sample rate to have a non-integer relationship to the input sample rate. The filter engine can be viewed conceptually as a fixed interpolate-by-32 filter, followed by an ...
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MSB = 0 SERIAL OUT 16 MSB = 0 μP (11 MANTISSA 4 EXPONENT NNNN EXP IFIR 24 24 QFIR AGC MULTIPLIER/SHIFTER † Controlled via microprocessor interface. In dB, this can be expressed as: ...
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The loop gain register values adjust the response/settling time of the AGC loop. The loop gain is set in the AGC Error Scaling circuitry, using four values in two sets of programmable mantissa and exponent pairs (see IWA register *010h). ...
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The median mode minimizes the settling time. This mode uses a fixed gain adjustment with only the direction of the adjustment controlled by the gain error. This makes the settling time independent of the signal level. For example, if the ...
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TABLE 2. MAG/PHASE ACCURACY vs CLOCK CYCLES MAGNITUDE PHASE ERROR ERROR CLOCKS (% f ) (DEG 0.065 3.5 7 0.016 1.8 8 0.004 0.9 9 <0.004 0.45 10 <0.004 0.22 11 <0.004 0.11 12 <0.004 0.056 13 <0.004 ...
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Serial Data Output Formatter Section ZERO I1 Q1 MAG R E PHASE GAIN STROBE ZERO NOTE: Each serial output has 7 time slots. Each slot can contain I1, Q1, I2, Q2, Mag, phase or dφ/dt. AGC gain, ...
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Serial Data Output Time Slot Content/Format Registers These four registers are used to program the content and format of the serial data output sequence time slots (see Microprocessor Interface section: Table 24, “SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA ...
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Microprocessor Interface 15:0 31: P(15: A(2: CLK CE (GATING NOT SHOWN) Data reads can be direct, indirect ...
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Read/Write Procedures To Write to the Internal Registers: 1. Load the indirect write holding registers at direct address ADD(2: and 1 with the data for the internal register ( bits depending on the internal register ...
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TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES ADD(2:0) PINS 0 WR Indirect Write Holding Register, Bits 15: Indirect Write Holding Register, Bits 31:16 Indirect Write Address Register for Internal Target Register (Generates a write strobe to transfer ...
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Tables of Indirect Write Address (IWA) Registers NOTE: These Indirect Write Addresses are repeated for each channel. In the addresses below, the * field is the channel select nibble. These bits of the Indirect Address select the target channel register ...
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TABLE 3. CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h) (Continued) P(15:0) 2 Enable COF/COFSYNC inputs. When set, this bit enables two bits from the D(15:0) input data bus to be used as a carrier offset frequency input. 1 Enable SOF/SOFSYNC ...
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TABLE 7. CARRIER NCO/CIC CONTROL REGISTER (IWA = *004h) (Continued) P(31:0) 2:1 Number of Carrier Offset Frequency (COF) serial input bits. The format is 2’s complement, early SYNC, MSB first Enable ...
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TABLE 13. FILTER COMPUTE ENGINE/RESAMPLER CONTROL REGISTER (IWA = *00Ah) (Continued) P(31:0) μPZ(4:0). These bits, when set to zero, zero the corresponding read pointer address bits. This allows the pointers to be aliased, i.e., 28:24 multiple filters can access and/or ...
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TABLE 15. WAIT THRESHOLD/DECREMENT VALUE REGISTER (IWA = *00Ch) P(31:0) μPTestBit. This bit is provided as a microprocessor controlled condition code for the filter compute engine for conditional execution 31 or synchronous startup. Active high. 30 Set to 0. 29:20 ...
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TABLE 22. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h) P(15:0) 15:11 Set to zero. μP AGC loop gain select Enable filter compute engine control of AGC loop gain. When this bit is set, bit which loop gain to use ...
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TABLE 23. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h) (Continued) P(31:0) 21:20 Magnitude output scale factor. The magnitude output of the cartesian to polar coordinate conversion has bits weighted as 0.- ...
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TABLE 24. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h) P(31:0) 31:24 Fourth serial slot in Serial Data Output 1 (SD1x See bits 7:0 for functional description of bits 31:24. 23:16 ...
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TABLE 26. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 1 (IWA = *017h) P(31:0) 31:24 Fourth serial slot in Serial Data Output 2 (SD2x See bits 7:0 of Table 24 for functional description of ...
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TABLE 31. FILTER COMPUTE ENGINE INSTRUCTION RAMS (IWA = *100h THROUGH *17Fh) P(31:0) 31:0 These locations in RAM are used to store the Filter Compute Engine instruction words. There are 128 bits per instruction word with each word consisting of ...
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Tables of Global Write Address (GWA) Registers NOTE: These Global Write Addresses control global functions on the HSP50216, so they are not repeated for each channel. The top five address bits select this set of registers (F8XXh). P(31:0) 31:17 These ...
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TABLE 36. BUS ROUTING CONTROL REGISTER (GWA = F801h) (Continued) P(31:0) 7 CH0 Ext AGC input enable. 0=CH0 loop filt, 1=external input. 6 CH1 Ext AGC input enable 0=CH1 loop filt, 1=external input. 5 CH2 Ext AGC input enable 0=CH2 ...
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TABLE 38. SERIAL CLOCK CONTROL REGISTER (GWA = F803h) (Continued) P(15:0) 2:0 SCLK rate. 000 Serial clock disabled. 001 Serial clock rate is Input CLK Rate. 010 Serial clock rate is Input CLK Rate/2. 011 Serial clock rate is Input ...
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TABLE 40. INPUT LEVEL DETECTOR CONFIGURATION REGISTER (GWA = F805h) P(31:0) 31:22 Set to zero Rectify input samples. Ones complement the 16-bit data after formatting if the value is negative. 0 Unmodified input Free run (ignore ...
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TABLE 45. μP FIFO READ ORDER CONTROL REGISTER (GWA = F820h THROUGH F83Fh) P(15:0) 4:0 The five bits selecting the data type are encoded as follows where CC is the channel number and DDD is ...
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... Lead BGA Package (Note 5 w/200 LFM Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . w/400 LFM Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CC = -40°C to +85°C, Industrial A SYMBOL TEST CONDITIONS ...
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T Electrical Specifications V CC PARAMETER MICROPROCESSOR WRITE TIMING P(15:0) Setup Time to Rising Edge of WR P(15:0) Hold Time from Rising Edge of WR A(1:0) Setup Time to Rising Edge of WR A(1:0) Hold Time ...
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Waveforms AIN, BIN, CIN, DIN, ENIA, ENIB, ENIC, ENID, SYNCI SYNCO, INTRPT RESET ADD(1:0) P(15:0) 49 HSP50216 1/f CLK CLK FIGURE 3. INPUT AND CONTROL TIMING t DSW t ...
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Waveforms (Continued ADD(1:0) P(15:0) CLK SCLK (/2 THROUGH /16) SYNC SDXX 50 HSP50216 ASR AHR t CSR t CHR FIGURE 5. MICROPROCESSOR READ TIMING SCLK (DIVIDE ...
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ROMd FIR Filters - Response Curves 0.0 -1.0 -2.0 -3 -6.0 0.0 0.1 0.2 0 FIGURE 8. CIC PASSBAND ROLLOFF ( STAGES DECIMATION FACTOR, ...
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ROMd FIR Filters - Response Curves 0 -20 -40 -60 -80 -100 -120 FREQUENCY (RELATIVE TO f NOTE: There is a 65dB limitation in SNR using the Re-Sampler Filter. FIGURE 13. ...
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FREQUENCY 5TH ORDER f /R PASSBAND ALIAS <-200 0.01 -0.007 -199.564 0.02 -0.029 -169.041 0.03 -0.064 -151.023 0.04 -0.114 -138.129 0.05 -0.179 -128.048 0.06 -0.257 -119.749 0.07 -0.351 -112.683 0.08 -0.458 -106.522 0.09 -0.580 -101.054 0.10 -0.717 ...
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TABLE 48. DECIMATING HALFBAND FIR FILTER COEFFICIENTS DECIMATING HALFBAND #1 (DHBF #1, 7-TAP) (DHBF #2, 11-TAP) COEFF HEX DECIMAL HEX C0 FBFE40 - 0.031303406 00C250 C1 000000 0.000000000 000000 C2 240100 0.281280518 F9B930 C3 3FFE80 0.499954224 000000 C4 240100 0.281280518 ...
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TABLE 49. INTERPOLATING HALFBAND FIR FILTER COEFFICIENTS INTERPOLATING HALFBAND #2 (IHBF #2, 15-TAP) COEFF HEX C0 FFAA24 C1 000000 C2 032B60 C3 000000 C4 F07F40 C5 000000 C6 4CAB00 C7 800000 C8 4CAB00 C9 000000 C10 F07F40 C11 000000 C12 ...
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COEFF HEX DECIMAL C 0/191 004000 0.001953125 C 1/190 006910 0.003206253 C 2/189 007A90 0.003740311 C 3/188 008C90 0.004289627 C 4/187 009ED0 0.004846573 C 5/186 00B0E0 0.005397797 C 6/185 00C230 0.005926132 C 7/184 00D240 0.006416321 C 8/183 00E090 0.006853104 C ...
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TABLE 51. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC GAIN ACCUM GAIN ERROR AGC LOOP BIT ERROR BIT FILTER GAIN POSITION INPUT WEIGHT (MANTISSA ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...