HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 37

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P(15:0)
P(31:0)
15:11
31:29
27:26
25:24
23:22
4:3
2:0
10
28
9
8
7
6
5
Set to zero.
μP AGC loop gain select.
Enable filter compute engine control of AGC loop gain. When this bit is set, bit
which loop gain to use with that filter output’s gain error. Setting bit 10 overrides this bit and forces a loop gain 1.
10:9
00
10
01
11
Mean/Median. This bit controls the settling mode of the AGC. Mean mode settles to the mean of the signal and settles asymptotically
to the final value. Median mode settles to the median and settles with a fixed step size. This mode settles faster and more predictably,
but will have more AM after settling.
1
0
Set this bit to 1 to get a dphi/dt output without having to feedback through the filter compute
Unused. Set to zero.
PhaseOutputSel
1
0
DiscShift(1:0). Shifts the phase up 0, 1, 2, or 3-bit positions, discarding the bits shifted off the top. This makes the phase modulo 360,
180, 90, or 45 degrees to remove PSK modulation. The resulting phase is 18 bits.
DiscDelay(2:0). Sets the delay, in sample times, for the dφ/dt calculation.
000
111
Set to zero.
Sync polarity
1
0
Reserved, set to zero.
Sync position. This applies to all time slots in the serial output. The Sync programming is associated with the SD1x serial output data
stream (x = A, B, C, or D).
00
01
1X
Reserved, set to zero.
FUNCTION
Loop Gain 0 (μP controlled)
Loop gain 1 (μP controlled)
Loop Gain controlled by filter compute engine
Loop 1 (μP override of filter compute engine)
Mean mode
Median mode
dφ/dt
Phase
1
8
Active low (low for one serial clock per word with a sync).
Active high.
Sync is asserted during the serial clock period prior to the first data bit of the serial word (early sync).
Sync is asserted during the clock period following the last data bit of the word (late sync).
Sync is asserted during the serial clock period of the first data bit of the serial word (coincident sync).
37
TABLE 23. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h)
TABLE 22. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h)
HSP50216
FUNCTION
FUNCTION
28
in the filter compute engine destination field selects
engine.
August 17, 2007
FN4557.6