R5F21294SNSP#U0 Renesas Electronics America, R5F21294SNSP#U0 Datasheet - Page 302

• Manufacturer Part Number: R5F21294SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21294SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
Figure 16.24
IIC bus Control Register 1
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate Exam ples for the
transfer rate. This bit is used for maintaining of the setup time in transmit mode of slave mode. The time is 10Tcyc
w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
Rew rite the TRS bit betw een transfer frames.
When the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
In master mode w ith the I
slave receive mode.
When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit is set to 0
and the IIC enters slave receive mode.
In multimaster operation use the MOV instruction to set bits TRS and MST.
Sep 26, 2008
b3 b2
ICCR1 Register
b1
b0
Bit Symbol
Symbol
ICCR1
RCVD
CKS0
CKS1
CKS2
CKS3
TRS
MST
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ICE
2
C bus format, w hen arbitration is lost, bits MST and TRS are set to 0 and the IIC enters
Transmit clock select bits 3 to
0
Transfer/receive select
bit
Master/slave select bit
Receive disable bit
IIC bus interface enable bit
(1)
(2, 3, 6)
Address
Bit Name
00B8h
(5, 6)
After reading the ICDRR register w hile the TRS bit
is set to 0
0 : Maintains the next receive operation
1 : Disables the next receive operation
0 : This module is halted
1 : This module is enabled for transfer
b3 b2 b1 b0
b5 b4
0 0 0 0 : f1/28
0 0 0 1 : f1/40
0 0 1 0 : f1/48
0 0 1 1 : f1/64
0 1 0 0 : f1/80
0 1 0 1 : f1/100
0 1 1 0 : f1/112
0 1 1 1 : f1/128
1 0 0 0 : f1/56
1 0 0 1 : f1/80
1 0 1 0 : f1/96
1 0 1 1 : f1/128
1 1 0 0 : f1/160
1 1 0 1 : f1/200
1 1 1 0 : f1/224
1 1 1 1 : f1/256
0 0 : Slave Receive Mode
0 1 : Slave Transmit Mode
1 0 : Master Receive Mode
1 1 : Master Transmit Mode
(Pins SCL and SDA are set to port function)
operations
(Pins SCL and SDA are bus drive state)
16. Clock Synchronous Serial Interface
After Reset
Function
00h
(4)
RW
RW
RW
RW
RW
RW
RW
RW
RW