R5F21294SNSP#U0 Renesas Electronics America, R5F21294SNSP#U0 Datasheet - Page 237

• Manufacturer Part Number: R5F21294SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21294SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
Figure 14.62
Figure 14.63
Timer RE Second Data Register
Timer RE Minute Data Register
b7 b6 b5 b4
b7 b6 b5 b4
Sep 26, 2008
b3 b2
b3 b2
TREMIN Register in Real-Time Clock Mode
b1 b0
TRESEC Register in Real-Time Clock Mode
b1 b0
Bit Symbol
Bit Symbol
TRESEC
TREMIN
Symbol
Symbol
MN00
MN02
MN03
MN10
MN11
MN12
SC00
SC01
SC02
SC03
SC10
SC11
SC12
MN01
BSY
BSY
Page 218 of 441
1st digit of second count bits
2nd digit of second count bits
Timer RE busy flag
1st digit of minute count bits
2nd digit of minute count bits
Timer RE busy flag
Address
Bit Name
Address
Bit Name
0118h
0119h
Count 0 to 9 every second. When the
digit moves up, 1 is added to the 2nd
digit of second.
When counting 0 to 5, 60 seconds
are counted.
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
Count 0 to 9 every minute. When the
digit moves up, 1 is added to the 2nd
digit of minute.
When counting 0 to 5, 60 minutes are
counted.
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
After Reset
After Reset
Function
Function
00h
00h
0 to 9
(BCD
code)
0 to 5
(BCD
code)
0 to 9
(BCD
code)
0 to 5
(BCD
code)
Setting
Setting
Range
Range
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO