R5F21294SNSP#U0 Renesas Electronics America, R5F21294SNSP#U0 Datasheet - Page 110

• Manufacturer Part Number: R5F21294SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21294SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
Figure 10.13
(flash memory operates)
(flash memory stops)
Wait mode
Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,
as described in Figure 10.13.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
FMR0 Register
FMSTP Bit
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
Sep 26, 2008
0
1
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
Time from Wait Mode to Interrupt Routine Execution
Interrupt request generated
activation sequence
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× 12 cycles + 30 µs (max.)
Flash memory
Time until Flash Memory
Period of system clock
Period of system clock
is Activated (T1)
T1
× 12 cycles
CPU clock restart sequence
Time until CPU Clock
Period of CPU clock
is Supplied (T2)
Same as above
× 6 cycles
T2
Period of CPU clock
Time for Interrupt
Same as above
Sequence (T3)
× 20 cycles
10. Clock Generation Circuit
Interrupt sequence
Following total
time is the time
from wait mode
until an interrupt
routine is
executed.
T3
Remarks