ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 69

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4
12.4.1
12.4.2
7701D–AVR–09/10
Register Description
MCUCR – MCU Control Register
PORTA – Port A Data Register
Table 12-9.
1.
2.
• Bits 7, 2– Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 6 – PUD: Pull-up Disable
When this bit is written to logical one, the pull-ups in the I/O ports are disabled even if the
DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See
Bit
Read/Write
Initial Value
Bit
0x1B (0x3B)
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
“Configuring the Pin” on page 56
EXT_OSC = crystal oscillator or low frequency crystal oscillator is selected as system clock.
EXT_CLOCK = external clock is selected as system clock.
PB1/XTAL2/PCINT9
EXT_OSC
0
EXT_OSC
0
EXT_OSC
0
0
EXT_OSC
PCINT9 • PCIE1
EXT_OSC
PCINT9 Input
XTAL2
PORTA7
Overriding Signals for Alternate Functions in PB1..PB0
R/W
R
7
–
0
7
0
(1)
(1)
(1)
(1)
(1)
PORTA6
+
• PCINT9 • PCIE1
PUD
R/W
R/W
6
0
6
0
Atmel ATtiny24/44/84 [Preliminary]
PORTA5
R/W
R/W
5
0
SE
5
0
for more details about this feature.
PORTA4
R/W
4
0
SM1
R/W
4
0
PB0/XTAL1/PCINT8
EXT_CLOCK
0
EXT_CLOCK
0
EXT_CLOCK
0
0
EXT_CLOCK
(PCINT8 • PCIE1)
(EXT_CLOCK
(EXT_CLOCK
CLOCK/PCINT8 Input
XTAL1
PORTA3
R/W
3
0
SM0
R/W
3
0
(2)
(2)
(2)
(2)
(2)
(2)
PORTA2
R/W
+ EXT_OSC
+ EXT_OSC
+ EXT_OSC
+ EXT_OSC
• PWR_DOWN ) +
• EXT_OSC
2
0
R
2
–
0
PORTA1
R/W
ISC01
1
0
R
1
0
(1)
(1)
(1)
(1)
(1)
+
• PCINT8 • PCIE1)
PORTA0
ISC00
R/W
0
0
R
0
0
MCUCR
PORTA
69