ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 124

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.2
124
Atmel ATtiny24/44/84 [Preliminary]
SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
The code is size optimized using only eight instructions (+ ret). The code example assumes
that the DO and USCK pins are enabled as output in the DDRE register. The value stored in
register r16 prior to the function being called is transferred to the slave device, and when the
transfer is completed, the data received from the slave is stored back into the r16 register.
The second and third instructions clear the USI counter overflow flag and the USI counter
value. The fourth and fifth instructions set the three-wire mode, positive edge shift register
clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times.
The following code demonstrates how to use the USI module as an SPI master with maximum
speed (f
SPITransfer:
SPITransfer_loop:
SPITransfer_Fast:
out
ldi
out
ldi
out
in
sbrs
rjmp
in
ret
out
ldi
ldi
out
out
out
out
out
out
out
out
out
out
out
out
out
out
out
sck
= f
ck
/4):
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
USICR,r16
r16, USISR
r16, USIOIF
SPITransfer_loop
r16,USIDR
USIDR,r16
r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
USICR,r16 ; MSB
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16 ; LSB
7701D–AVR–09/10