ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 161

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Atmel ATtiny24/44/84 [Preliminary]
The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during
the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to logical one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes a page erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion
of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire page erase operation.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to logical one
together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have
a special meaning (see description above). If only SPMEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion
of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During
page erase and page write, the SPMEN bit remains high until the operation is completed.
Writing any combination other than "10001", "01001", "00101", "00011", or "00001" in the
lower five bits will have no effect.
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