ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 116

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.11.4
14.11.5
14.11.6
116
Atmel ATtiny24/44/84 [Preliminary]
TCNT1H and TCNT1L – Timer/Counter1
OCR1AH and OCR1AL – Output Compare Register 1 A
OCR1BH and OCR1BL – Output Compare Register 1 B
A FOC1A/FOC1B strobe will not generate any interrupt, nor will it clear the timer in clear timer
on compare match (CTC) mode using OCR1A as top. The FOC1A/FOC1B bits are always
read as zero.
• Bit 5..0 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must
be written to logical zero when the register is written.
The two timer/counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access for both read and for write operations to the timer/counter unit's 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
16-bit Registers” on page
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a
compare match between TCNT1 and one of the OCR1x registers.
Writing to the TCNT1 register blocks (removes) the compare match on the following timer
clock for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The output compare registers are 16 bits in size. To ensure that both the high and low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all
the other 16-bit registers. See
Bit
0x2D (0x4D)
0x2C (0x4C)
Read/Write
Initial Value
Bit
0x2B (0x4B)
0x2A (0x4A)
Read/Write
Initial Value
Bit
0x29 (0x49)
0x28 (0x48)
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
93.
“Accessing 16-bit Registers” on page
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
OCR1A[15:8]
0
4
OCR1B[15:8]
0
TCNT1[15:8]
OCR1A[7:0]
OCR1B[7:0]
TCNT1[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
93.
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
7701D–AVR–09/10
“Accessing
OCR1AH
OCR1AL
OCR1BH
OCR1BL
TCNT1H
TCNT1L