C8051F018-GQ Silicon Laboratories Inc, C8051F018-GQ Datasheet - Page 76

• Manufacturer Part Number: C8051F018-GQ
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1197

11.1.
The C8051F018/9 incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above
the V
Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the 100ms
VDD Monitor timeout in order to allow the VDD supply to become stable.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset
flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to
determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be
undefined after a power-on reset.
11.2.
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 11.1.
11.3.
When a power-down transition or power irregularity causes VDD to drop below V
will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 11.2). When VDD returns to a level
above V
though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD
dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
RST
Logic HIGH
Logic LOW
RST
Power-on Reset
Software Forced Reset
Power-fail Reset
level during power-up. (See Figure 11.2 for timing diagram, and refer to Table 11.1 for the Electrical
, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even
2.80
2.40
2.0
1.0
/RST
V
RST
Figure 11.2. VDD Monitor Timing Diagram
100ms
Rev. 1.2
RST
, the power supply monitor
C8051F018
C8051F019
100ms
t
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