C8051F018-GQ Silicon Laboratories Inc, C8051F018-GQ Datasheet - Page 139

• Manufacturer Part Number: C8051F018-GQ
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1197

18.1.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and
load it into the corresponding module’s 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn
and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-
high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative
edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt
request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software.
139
Port I/O
C8051F018
C8051F019
Crossbar
CEXn
Figure 18.3. PCA Capture Mode Diagram
PCA0CPMn
E
C
O
M
n
0
Rev. 1.2
C
A
P
P
n
C
N
A
P
n
0
1
M
A
T
n
0 0 0
O
G
T
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
C
C
F
4
C
C
F
3
PCA
Timebase
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H